May 21, 2007
DAC & DFM – Once More, with Feeling
Please note that contributed articles, blog entries, and comments posted on are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor

by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Rob Aitken – No, ARM is a DFM user and includes DFM as part of its physical IP products.

Srini Raghvendra – Yes.

Sudhakar Jilla – We are a DFM-only vendor. We address DFM as a part of place and route.

Tom Wong – Takumi Technology is a DFM vendor. Takumi offers software that can automatically repair hot spots on GDSII layouts by leveraging manufacturing data to address hot spots on cell and full-chip designs to improve device performance and yield. Takumi also offers design-driven defect analysis software for mask-defect analysis.

Yervant Zorian & Ken Potts – In the traditional EDA sense, no, we are not a DFM tool vendor. Virage Logic is part of the DFM ecosystem. The company provides the STAR Memory System that drastically improves SoC manufacturability and yield optimization. Customers such as Agere have seen yield improvements of up to 250 percent using the STAR Memory System.


3) In 20 words (max!), what does your tool do?

Atul Sharan – Clear Shape's InShape/OutPerform enable designers to perform variability-aware analysis and optimization based on true silicon behavior, maximizing process technology utilization.

Chenmin Hu – NanoScope is a pattern-centric platform with model-based simulation that enables hot-spot identification and layout optimization at design and manufacturing steps.

Dave Holt – see #2.

Dave Reed – Blaze MO dramatically reduces leakage power on sub-100 nanometer chips without requiring major disruptive changes to the design flow.

Joe Sawicki – Calibre nm platform provides user interface/data integration foundation for DFM toolset: physical verification, RET, OPC, MDP, design-centric tools (hot-spot detection, CMP analysis/fixing, CAA/fixing, critical feature analysis/fixing).

John Lee – Physical and electrical DFM prevention, correction, and analysis.

Kamal Aggarwal – Nirmaan, is a software development toolkit that enables semiconductor companies to develop post-layout DFM tools. We also offer tools for layout/mask data compression, comparison, and translation.

Michael Buehler-Garcia – Ponte provides solutions that allow designers, etc., to assess the impact of process variability and customize their DFM rules accordingly.

Mitch Heins – Our tool takes into account manufacturing models DURING the physical design flow to produce optimal routing QoR [Quality of Results], particularly on performance and yield.

Prashant Maniar – Our suite of products characterizes and models parametric variability and utilizes these statistical models to analyze a circuit’s statistical performance.

Srini Raghvendra – Our PrimeYield tool suite analyzes designs for DFM issues such as litho, stress, and CMP, and links to upstream design tools to help fix the problems.

Sudhakar Jilla – It is a P&R system which addresses variations in design modes, process corners, and lithography/CAA [critical area analysis].

Tom Wong – Takumi Enhance improves yield using automated, cost-aware, 2D layout optimization that can analyze, trade-off, and fix various layout hot spots.

Yervant Zorian & Ken Potts – Our system, the STAR Memory System, performs diagnostics, debug, and repair to improve reliability, manufacturability and yield.


4) When was the last time you talked to a real designer?

Atul Sharan – Today. Also, yesterday, and the day before. I talk to designers every day.

Chenmin Hu – We are constantly talking to designers to get their feedback on our products. We talked to them as recently as this week.

Dave Holt – Today. We have several ongoing projects at 65 nanometers and 45 nanometers with large IDMs (“real designers” in your parlance) using our mask-reconfigurable IP. There are multiple program reviews with different customers each week (2 different customer meetings this morning, for example).

Dave Reed – Today. We are in constant contact with our customers and talk to them everyday.

Gary Smith – Today at 5:45.

Joe Sawicki – We are in constant contact with our large installed base of physical verification (Calibre) tool users, which includes designers who must achieve DRC-clean designs. Our installed base includes foundries, IDMs, and fabless design houses. It’s our interaction with these users that enables us to identify new challenges and needed capabilities to provide manufacturing process insight back to designers, so they can take focused action to improve yield through design improvements.

John Lee – Today.

Kamal Aggarwal – As a software toolkit provider, we regularly speak to our immediate customers that are in-house EDA groups in semiconductor, mask makers, or foundries. We also interact regularly with the end users of our tools which are tapeout engineers in IDMs, mask makers, foundries. As part of the side of our business, which is custom tool development for specific requirements of semiconductor companies, we talk to designers for their unique and emerging needs.

Michael Buehler-Garcia – Every day! Ponte has paying customers using our products at multiple customer sites.

Mitch Heins – We talk to them every day, as we firmly believe that great tools can only be developed with actual designs and real user feedback.

Prasad Subramanian – We are designers.

Prashant Maniar – Today. Our company philosophy is to engage early adopter customers right from the development of the product concept, and to continue receiving feedback at every stage of product and business development.

Rob Aitken – Today.

Srini Raghvendra – A few days ago. We are in constant touch with a number of leading-edge designers.

Sudhakar Jilla – We talk to our customers, i.e. designers, on a daily basis.

Tom Wong – Yesterday. We have worked with customers on a daily basis over the past three years since the company was founded. Companies such as Renesas, Toshiba, and NEC have deployed Takumi products into production.

Yervant Zorian & Ken Potts – The precise answer is today. However, that is only a piece of the story. The ecosystem requires that the ongoing dialogue be between the manufacturing domain, the design domain, and the IP domain. This dialogue enables the expertise of each area to integrate and then manifest as value to the designer. In the case of Star Memory System, designers use our tool everyday to improve their time to volume.


5) When was the last time a real designer used your tool?

Atul Sharan – The same answer as #4. Today.

Chenmin Hu – We have designers that are using our tools on a daily basis to analyze DFM issues to get improvement on yield.

Dave Holt – Today.

Dave Reed – Today. We have numerous customer engagements in process right now, and are continually adding new names to our growing list of customers. Our first customer tapeout was in November 2005; first customer silicon was in March 2006.

Joe Sawicki – All three areas of DFM tools from Mentor (physical verification, manufacturing for design, and design centric) are being used daily by real designers on real designs at leading IDMs, fabless design houses, and foundries. In physical verification, Calibre is the industry leading tool for DRC sign-off. In MFD, Calibre nmOPC and OPCverify are among the leading computational lithography solutions. Mentor design-centric DFM tools are broadly deployed at leading companies such as AMD, UMC, Infineon, Chartered, IBM, and STARC.

John Lee – Today. We have production users at top customers worldwide.

Kamal Aggarwal – Since our core product, Nirmaan, is in the post-layout DFM space, a conventional RTL-to-GDSII designer does not use our product. However, our layout/mask-data translation and compression tools are used by physical design engineers. Our customized tools, developed as part of our customized tool development services, are used by designers across the design flow, from system level down to physical design.

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-- Peggy Aycinena, Contributing Editor.


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