May 14, 2007
Patent Licensing – MOSAID Technologies
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Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

NVIDIA and Broadcom joined to showcase the 3D graphics, wireless, battery life, and compute performance advantages of next-generation AMD mobile platforms. Based on superior technologies from the AMD Better by Design program -- including next-generation 65nm AMD Turion 64 X2 dual-core mobile technology, chipsets from AMD and NVIDIA, and leading wireless networking solutions from Broadcom -- these mobile platforms deliver a superior Windows Vista experience for end-users. AMD's leading-edge Better by Design ecosystem includes ATI Radeon and NVIDIA GeForce Go graphics and wireless solutions from Atheros, Broadcom, Marvell Qualcomm and RealTek.

Maria M. Pope will join the company as vice president and chief financial officer, reporting to president, Gregory K. Hinckley. Pope will be responsible for treasury, tax, accounting, internal audit, corporate development, and investor relations at the company. Additionally, she will manage facilities and purchasing.

Previously, Pope held various senior management positions at Pope & Talbot, Inc., most recently vice president and general manager of the Wood Products Division. She has also held financial management positions at Levi Strauss & Co. and at Morgan Stanley & Co.

Originally announced in June 2006, AC datatypes are arbitrary-bit-width datatypes based on ANSI C++. They enable algorithm, system and hardware designers to precisely model bit-true behavior in C++ specifications while accelerating simulation speeds by 10-200x faster versus alternate datatypes.

Other EDA News

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  • Cadence Extends Verification Resources With New Plan-to-Closure Methodology Qualified Program  
  • ISQED Announces 7 Recipients Of The Prestigious Honorary Fellow Awards  
  • Mentor Graphics Announces Synthesis Support for New Altera Arria GX FPGA Family  
  • MOSAID and LSI Sign Exclusive Patent Licensing Agreement  style="mso-spacerun: yes"> 
  • Flomerics Releases Flotherm Version 7 with Unrivalled Design Optimization Capability  
  • Silicon Image Announces Upcoming Investor Event Webcast  style="mso-spacerun: yes"> 
  • Altera Introduces Arria GX Family of Low-Cost, Transceiver-Based FPGAs    
  • Achieve 2X Faster Compile Times and Half the Memory Footprint With Altera Quartus II Software v.7.1    
  • TRADE NEWS: Agilent Technologies Announces Strategic Partnership With Mentor Graphics on Automotive Network Design, Test and Validation Tools    
  • Dongbu HiTek Adopts Legend Design Technology's Memory Characterization Tools for Quality Timing and Power Models    
  • Achronix and Mentor Graphics Announce Joint Agreement    
  • CebaTech Joins Chip Estimate's Prime IP Partner Program    
  • Bluespec Adds System-Level Building Blocks to AzureIP Foundation Library    
  • Synopsys Design Compiler Topographical Technology Adopted by IBM to Accelerate ASIC Designs for Customers    
  • EDA Consortium Panel: "What Customers Want for Hardware-Software Co-Design Tools"    
  • The MathWorks and Analog Devices Introduce Link for Analog Devices VisualDSP++    

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    -- Jack Horgan, Contributing Editor.


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