May 07, 2007
DATE 2007 Part 2 – Special Days, Frustrating Hours
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Peggy Aycinena - Contributing Editor

by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

5) The bios provided to me were too long. Reading six long bios aloud is perfect, if you want to put a late-afternoon panel audience to sleep before the panel has even started.

6) Mr. 13 was unfortunately first in the opening statement queue. His ponderous presentation ran so long and was so laden with marketing, one of the other panelists lashed out and told him to cut it short. A first in my experience.

7) The opening statements chewed up 60 minutes of the 90 minutes allotted for the panel session. Mr. 13 having had so much time, it was not possible to cut the others short.

8 ) Irritated and frustrated, I took the mic down into the front row of the audience to lob questions at the panelists after the 6 opening presentations were finally done. I did not see that there were hands raised in the audience behind me. Therefore, there was no Q&A between the panelists and the audience.

9) On the eve of the French elections (just 3 days later), the most controversial of the French candidates, Jean-Marie Le Pen, was due to arrive at the Acropolis Convention Center for a rally in the theater just 30 minutes after our panel was due to wrap up. We had been advised there might be a police cordon around the building and/or street demonstrations to wade through in order to leave DATE. That did not make the panelists happy, nor was I pleased with the news.

In short, a disaster. I was honored to have been asked to be part of the Special Day program, but the end result of months of effort was disheartening. Would that I could re-do this panel. So much more could have been accomplished.


Lest I appear to end my report on DATE 2007 on a negative note, let me emphasize – this is an important conference in the life of the design automation and test industries. There was substantive conversation taking place in many quarters at DATE, with a particular and elucidating emphasis on systems and software. The DATE Committee has a great deal to be proud of, in the organization, and depth and breadth of the content of the program.

Those who were able to attend in Nice learned a great deal. They should return for DATE 2008 – next year in March in Munich – and they should be joined there by anyone who is interested in pushing the envelope and furthering the conversation about the future of the technology and the industry.

See you all there!


More news from DATE and beyond …

Altos Design Automation announced that
Global Unichip Corp. has adopted Altos’ Liberate library characterization product. Global Unichip says it is using Liberate to re-characterize 90-nannometer low power standard cell library at a lower supply voltage. The re-characterized library is to be applied to portable applications.

Bluespec and
EVE announced what the companies call “an integrated solution” of ESL synthesizable transactors and models that run directly on EVE’s hardware-assisted verification platforms. Per the Press Release: “The link between Bluespec’s ESL synthesis and EVE’s ZeBu hardware-assisted verification platform of accelerators, emulators and FPGA prototypes offers high simulation speed with hardware accuracy early in the development cycle for architectural exploration, virtual prototyping, modeling and verification. The result is a single development environment for models, transactors, implementations and synthesizable verification testbenches, and a
rich foundation library of IP.”

Bluespec also announced new “system-level building blocks” in its AzureIP Foundation Library. New blocks include ARM AMBA AXI and AHB, and OCP-IP interface bus component libraries with parameterized bus structures, bus interface transactors, and data-type libraries. Per the Press Release: “Falling between low-level IP components such as adders and multipliers and large IP blocks including Ethernet, PCI, H.264 and processors, these blocks fill a void in the middle of the IP space … At the heart of Bluespec’s’ bus fabric IP offering is a unique Transaction Level Modeling (TLM2) bus payload data structure and protocol. This generic
representation supports multiple bus protocols and is based on the OSCI TLM 2.0 draft specification.”

Cadence Design Systems reported Q1 2007 revenue of $365 million, an increase of 11 percent over the $328 million reported for the same period in 2006.

Chip Estimate Corp. announced an online newsletter for designers using SIP in their chip designs. The newsletter contains information on the IP available from various supplies, plus a column on IP and design topics.

CoFluent Design announced that CoFluent Studio has been selected as part of the CIM PACA collaborative research platform. CIM PACA (Centre Integre de Microelectronique Provence Alpes Côte d'Azur) members include Atmel, NXP, STMicroelectronics, Texas Instruments, the University of Nice, and other public research labs, and offers three collaborative research platforms for the development of microelectronics applications. CoFluent Studio is part of the Design platform as architecture exploration and performance analysis solution. The goal of the CIM PACA Design platform is to offer to the local industrial and academic community the tools and techniques allowing them to
address the challenges of the design of integrated circuits for the next decade in the field of secured communicating solutions.

DATE conference organizers announce final attendance numbers: 1641 conference delegates, 2171 exhibition visitors, 30 members of the press, 1080 exhibitor personnel, 4922 total registrations. The geographic breakdown: European attendees, 76% (France at 27%, Germany at 14%, UK at 6%), North and South Americas at 16%, Middle East and Asia at 8%.

EVE announced its ZeBu-AX hardware accelerator, a result of the company’s acquisition of
Tharas Systems Inc. earlier this year. EVE says a full product roadmap with details about its family of accelerators, fast emulators, and prototyping solutions will be unveiled in June 2007. Meanwhile, per the Press Release, “ZeBu-AX offers plug-and-play, event-accurate mixed-language simulation acceleration. A scalable capacity lets ZeBu-AX handle designs that can reach up to 512-million ASIC gates. Its one-pass compilation executes at a speed of 125-million ASIC gates per hours on a single workstation, mapping onto the accelerator for design-under-test, and a significant portion of the behavioral testbench. The process is fully automatic and does not require user
intervention. Its single-kernel runtime environment works in co-simulation with
Synopsys VCS,
Mentor Graphics QuestaSim,
Cadence NC-Sim.”

EVE also announced it ended its fiscal year March 30, 2007 with revenue growth of 115%, and has reached five consecutive quarters of profitability.

IC Manage announced its Global Design Platform (GDP), which the company says is “the first data management solution to offer design assembly, derivative management, and real-time worldwide delivery … GDP enables companies to efficiently manage, locate, assemble and reuse design data and IP across the enterprise during all phases of the design process.”

Impinj, Inc. announced the company’s AEON/MTP Parallel Architecture memory core now meets TSMC quality standard and, per the Press Release, “achieved silicon validation in TSMC’s 0.18-micron process and is the first NVM multiple-time-programmable (MTP) IP product to meet the foundry’s reliability, performance and manufacturing standards. Used to store up to 128 bits of crucial on-chip data, such as encryption keys for digital media applications and electronic product code data in RFID tags, AEON/MTP is the world’s first MTP NVM product line manufactured in standard logic CMOS processes.”

Key Stream Corp. announced the company is using Sequence Design’s PowerTheater to reduce power early in the design cycle at RTL. Key Stream is designing 802.11a/b/g wireless LAN chipsets, primarily for emerging portable applications.

Kilopass Technology and
Chip Estimate Corp. announced that Kilopass has joined the Chip Estimate Prime IP Partner program. Kilopass IP can now be searched for and used in chip plans for free at the Chip Estimate website.

Magma Design Automation reported revenue of $50.1 million, an increase of
13.9 percent over the $44.0 million reported for the year-ago fourth quarter, ended April 2, 2006. Magma reported revenue of $178.2 million for the fiscal year, an increase of
8.6 percent over the $164.0 million the company achieved in fiscal 2006, ended April 2, 2006.

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-- Peggy Aycinena, Contributing Editor.


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