April 30, 2007
Device Native Verification of FPGAs - GateRocket
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How big a company is GateRocket?
We have 6 fulltime employees and a host of consultants. I have established a network of value added resellers to sell this product across the nation. This year we are focusing mainly in North America. Our plans show us expanding internationally in ’08 from a sales point of view.
What is the challenge that GateRocket faces?
Part of the challenge in being an EDA company is that the majority of the attention is given to the ASIC design flow. Unfortunately not many people focus on the FPGA. The trends are staggering. There are 15 times the design starts for FPGAs than there are for ASICs. ASIC starts are in the range of 3,000 starts annually. According to Gartner they are expected to stay in that range through 2010 while FPGA starts are expected to grow in that same period. We as a company focus on large FPGAs. I would define large as anything greater than 40,000 logical elements which frankly is relatively small but it is large enough that people with designs that size are experiencing these problems. Simulation is just too slow. People building systems with FPGAs are now running into the same problems that ASIC designers are. FPGAs are now the modern ASICS. People who use chips to consolidate logic or design new systems are implementing in FPGAs first as a methodology of getting to market faster. Simulation is too slow and by and large can be inaccurate. When we simulate a design, we simulate a model. The simulation results are only as good as the models are. In my experience when I talk with our early customers about their experiences, every single customer to a man says that they are utilizing some third party IP and the behavior of that IP under simulation is different
from the IP on the actual FPGA. Companies are frustrated by that problem. When I say inaccurate, I am not saying that simulation does not work. That is not true at all. It works bit it is only as good as the models you give it. If what they are designing does not behave on the physical chip the same way as it does in simulation then as far as the designer is concerned it is inaccurate. If the simulation for a single chip is slow, then designs with multiple chips are far too complex for simulators to handle. Nowadays systems have multiple FPGAS and companies want to be able to validate these designs.
I can’t mention the name of the company but I had a discussion with a prospect who has a board and they are in the process of respinning one of the ASICs on that board that has been around for years. The plan is to respin the ASIC into an FPGA. The guy said that the goal for doing that was to reduce the power dissipation of the overall board. It turns out that with some of the new FPGA technology, FPGA vendors have the opportunity to take advantage of deep submicron technology and deliver a standard part. As new FPGAs come out they are consuming less power. If I compare an old ASIC to a new FPGA they have the ability to respin an old ASIC with a new FPGA and eliminate the cost of
the NRE. I though that was an interesting story. Obviously, if you compare gate for gate, a modern 65 nm ASIC versus a 65 nm FPGA, the ASIC will consume less power. But a lot of companies are factoring in multiple dynamics in their decisions. They factor in the cost of NRE, multiple spins and the time it takes to get there.
If I look at an ASIC design, a designer gets to the point where he has a simulation model of the design and he has a test bench. He is able to test all the paths to the point where he can declare that he has a known good design and now needs to iterate through synthesis and place and route until he gets a known good chip. The ASIC designer starts with a known good design and iterates to get a known good chip. For the FPGA designer the whole process stands on its head because eh FPGA vendors like Xlinix and Altera give the designer a known good chip and he or she has to iterate until they get a known good design on the FPGA. The problem is flipped. The fact that we have a programmable
chip gives us a lot of opportunity to create products.
What is the product that you are launching?
We are introducing RocketDrive. It is a solution for faster, more accurate FPGA verification. We deliver depending upon design size 10 to 100 times simulation acceleration with the same behavior as the target FPGA family. At launch we are supporting Xlinix and Altera. It is a scaleable system. We can provide verification for up to 8 simultaneous RocketDrives. This is not a solution that eliminates the simulator. It complements and supplements the simulation environment. There is no methodology change. It is easy to integrate into the existing environment. There are only minor changes in the test benches. We have a philosophy about our product that it is very easy to use, something that
fits into existing methodology and adds value without forcing anyone to change methodology or approach. The other thing we have done is gotten very creative with the form factor of the product. It looks like it would fit in a standard ¼” PC form factor and it does. We install this RocketDrive into any Linux PC that the customer has. It interfaces through a PCI card. Our software is economically priced. We want to be very aggressive with respect to the market and help people leverage these as quickly as possible.
One thing I will tell you to eliminate possible confusion is that even though we call it RocketDrive there is no hard disc in it. Inside the RocketDrive we put the largest FPGA in the FPGA family of Altera or Xilinx. The electronics provides accessibility to to integrate that FPGA with the customer’s simulator. In essence what we are doing is connecting or bringing the FPGA device into the loop of simulation. That’s why we call it Device Native verification. You can think about it that any part of the design that the customers place onto the FPGA in the RocketDrive compared to software simulation. The premise is that the customer can move what he wants from his simulator or the RocketDrive to get acceleration for that part. He sees the actual behavior of how the device will work when it winds up in the system. He is seeing the behavior of the design not in simulation but on the chip. Obviously if you have a system with multiple FPGAs on it, he can implement a system with multiple RocketDrives that are connected to a simulator. Think of the simulation test bench environment that the customer has as an infinitely flexible virtual prototype environment. The simulation test bench is like a virtual printed circuit board that provides the connection between one or more RocketDrives and the test that the customers wants to run against the design. In essence
that’s what the RocketDrive is all about.
Any design nowadays has multiple elements of third party IP, logic, a processor and other components. Customers are generally using one of the top simulators; Cadence or Synopsys. We integrate the RocketDrive into the simulator and we utilize the largest members in the Xilinx or Altera family. The customer can decide which portions of the design to place in the RocketDrive. If I am doing a new design and someone has given me some IP that I have never seen before, I can move this IP and its testbench alone into the RocketDrive and see if it behaves the same way as the simulation model and what kind of behavior I am getting from the IP on the RocketDrive. Or I can put the entire design in
the RocketDrive and see how it works. Before I get into the lab with the end product chip on a board, I really do not have the tools to see what is going on. I can actually validate how the design is going to work on the chip.
Another use model that we believe people will want to utilize is for doing a new design that is a derivative of an old design. Let’s say three quarters of the design is from an old design. In that case I would put the three quarters onto a RocketDrive and I keep the part that I am iterating within the simulator. I am always comparing the piece I am changing to the part that is running and behaving as it would on chip. I am getting acceleration for that part of the design so my productivity is better. I am comparing against everything else but I got the productivity of iteration of the actual simulator.
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-- Jack Horgan, EDACafe.com Contributing Editor.
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