January 08, 2007
Changes at MoSys
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Your website lists as partners a number of foundries.  In what sense are they partners?

Some of them have technology licenses.  All of them have to qualify the technology on advanced technology nodes.  We work with their sales force to talk to our mutual customers and prospects about the technology.

The top articles over the last two weeks as determined by the number of readers were:

Incentia’s TimeCraft Advanced On-Chip-Variation Timing Analysis Adopted by Faraday  Incentia Design Systems, Inc., an EDA software company that focuses on the timing and synthesis market, announced that Faraday Technology Corporation, a leading provider of ASIC design services and silicon IPs, has adopted Incentia’s TimeCraft advanced On-Chip-Variation (OCV) solution to improve its timing analysis efficiency and accuracy with Faraday’s advanced
Location, Level, and Cell-Based On-Chip-Variation (LLC-OCV) libraries.  TimeCraft is a full-chip, gate-level STA for timing signoff. It features comprehensive timing checking and reports, a built-in delay calculator, multiple supply voltage analysis, multi-task capability for multi-corner and multi-mode analysis, and advanced PLL handling, which enable the analysis on a large variety of design styles. TimeCraft has the runtime and capacity advantages that can dramatically reduce timing verification turnaround time.

Cadence CEO Michael J. Fister Joins SynapSense Board of Directors  Fister, named Cadence CEO in May 2004 after a 17-year career at Intel Corporation, joins the SynapSense Board of Directors with CEO Peter Van Deventer and Chief Technology Officer Dr. Raju Pandey; Corley Phillips, Managing Partner of American River Ventures; and Rodrigo Prudencio, a Partner with Nth Power.

Bluespec Begins Volume Shipment of SystemC Synthesis ESEComp is the first ESL control logic synthesis software to support the SystemC language. It allows models and designs written at a high-level, including complex control and datapaths, to be generated into efficient RTL code. As a SystemC-based synthesis tool, it unifies architecture modeling, software prototyping and implementation at a high-level of abstraction, and is the only general purpose
SystemC synthesis solution bridging ESL and RTL.

There is a free download of the ESL Synthesis Extensions (ESE, pronounced csc) to SystemC available through Bluespec's website (http://www.bluespec.com). This free version supports the ESL Synthesis language extensions for untimed simulations with the standard OSCI SystemC simulator.

ESEComp supports Red Hat Linux operating systems.

EVE Survey of DAC Attendees Finds Most Satisfied with Verification Environment  In a survey DAC attendees taken during the conference in July, EVE found that 60 percent of respondents were satisfied with their current verification environment. Of 617 surveys collected during the four-day conference, 477 were used to compile the survey.

Among the findings, close to 60 percent of respondents said that their design team performed hardware/software co-verification, and 55 percent use or plan to use hardware-assisted verification. The survey showed trends toward bigger designs -- 72 percent noted that their designers were larger than two million gates -- and a growing need for better performance or software development, leading to a strong desire for hardware-assisted verification solutions.

Cadence Pharmaceuticals Initiates Pivotal Phase III Clinical Trial Evaluating Intravenous Acetaminophen for Post-Operative Acute Pain 
Cadence Pharmaceuticals, Inc. (NASDAQ: CADX), a biopharmaceutical company focused on in-licensing, developing and commercializing proprietary product candidates principally for use in the hospital setting, today announced it has begun dosing subjects in a Phase III clinical
trial to evaluate intravenous acetaminophen (IV APAP) for the treatment of post-operative acute pain. The pivotal trial, referred to as CPI-APAP-301, is the second trial initiated as part of Cadence's clinical program to evaluate the efficacy and safety of IV APAP for pain and fever in adults and children. IV APAP has been marketed by Bristol-Myers Squibb Company in Europe since mid-2002, where it is now the market leader among injectable analgesics.

Cadence Design Systems Announces Intention to Offer $500 Million Senior Convertible Notes
Cadence announced its intention to commence an offering, subject to market and other conditions, of $250 million principal amount of convertible senior notes due 2011 and $250 million principal amount of convertible senior notes due 2013.  Cadence intends to use up to approximately $200 million of the net
proceeds of this offering to repurchase a portion of its zero coupon zero yield senior convertible notes due 2023 and a portion of the net proceeds to fund the cost of the convertible note hedge transactions described below. Cadence intends to use the remainder of the proceeds from the sale of the 2011 and 2013 notes to purchase shares of its common stock.


Other EDA News

  • The MathWorks Adds Support for Signal Integrity Engineering to RF Toolbox

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    -- Jack Horgan, EDACafe.com Contributing Editor.


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