October 16, 2006
Chipidea - Analog and Mixed-Signal IP
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

What information is downloadable from your website?

You have a product overview, normally one to two pages of information. After sending in a non-disclosure agreement, we can send technical information. We can put the customer/prospect in contact with engineering.

What about your IP demonstration boards?

They are mostly for USB. We have boards we can ship to our customers for evaluating. That's basically it. We have more than 400 IP products. It is not practical to make boards for everything. USB is our most popular IP. It accounts for about one third of our revenue. We have much more marketing material prepared in this area.

Over the next two to three years, where do you see the growth coming from for Chipidea?


Would you give us a quick summary?

We have introduced a new line of sigma-delta ADCs with which we can support our customers in the embedded IP market. It is a very mature IP. We offer low risk and fast time to market. They are highly optimized for high resolution and low power. They are highly programmable so that we can support multiple applications with the same IP.

The top articles over the last two weeks as determined by the number of readers were:

Anchor Semiconductor Closes 2nd Round Financing for Design for Manufacturing Business Expansion Anchor Semiconductor closed its second round of financing in the amount of $7.2 million. H&Q Asia Pacific led the financing. This new infusion of funds will be used to significantly grow R&D, applications engineering, sales and the marketing team.

Calypto Design Systems Expands European Presence Bill Campbell will lead efforts to expand Calypto's European market presence. He brings more than 20 years of EDA sales and marketing experience from Synopsys, Tensilica, Avant! and Chrysalis. Most recently, Bill was CEO of Microemissive Displays Ltd. which developed LED on CMOS microdisplays. Calypto also announced it has signed an agreement with the ISS Group to distribute Calypto products throughout the Nordic region.

Cadence Develops Lithography-Aware Design Flow in Collaboration With Brion and Clear Shape Cadence announced that it has created a lithography-aware design flow and has defined an interface that will link resolution enhancement technologies (RET) with physical design and verification. Cadence has collaborated with Brion Technologies and Clear Shape Technologies in developing this flow which addresses critical lithography-induced yield problems and mask-design challenges. Clear Shape has developed DFM technologies for fast and accurate systematic, full-chip, model-based manufacturing shape
analysis for both catastrophic and parametric issues. Brion Technologies has leveraged its computational lithography technology to deploy an accurate, fast, full-chip optical proximity correction (OPC) and OPC verification solution. By linking either company's technologies with the Cadence Encounter digital IC design platform including Cadence Chip Optimizer using the newly defined interface, Cadence provides customers with an integrated lithography modeling, design implementation and layout optimization flow.

Apache Design Solutions Announces Expansion of India Operations The Indian unit located in Bangalore will continue to provide customer support while leveraging India's elite engineering expertise. Apache Design Solutions increased its headcount by over 400% in 2006 and plans to double the current headcount in 2007. Prashant Pahade will manage Apache's office in Bangalore. Pahade comes to Apache with over fifteen years of EDA experience, most recently at Cadence where he served as Sr. Global Account Executive, North America Sales responsible for six global accounts. Before joining Cadence,
Pahade was CEO and founder of Gizmo123.

Accellera Continues to Promote Increased Electronic Design Productivity With Revised VHDL Standard Accellera, announced that its members and Board of Directors have approved a revised version of the VHDL specification. The revision integrates the Property Specification Language (PSL), adds IP protection methods and offers improvements that increase designer productivity.

In July, the organization announced approval of the VHDL API standard known as VHPI. Both standards have been transferred to the IEEE for their consideration as revisions to the VHDL standard, IEEE Std. 1076™-2002.

Other EDA News

Other IP & SoC News

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-- Jack Horgan, EDACafe.com Contributing Editor.


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