October 02, 2006
MathWorks: Simulink HDL Coder
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Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

What are the key features of Simulink HDL Coder?

It synthesizes both the HDL and Verilog. There are about 80 Simulink blocks for data path in V1.0. Control logic is handled by the Mealy and Moore state machines that are modeled in the Stateflow product. These are the typical finite state machines elements that are used in hardware implementations. The code is technology independent, device independent, bit exact and cycle accurate implementation of the model.

In addition to synthesizable code we also generate the HDL testbench. The engineer has already created the testbench in the model and that testbench can be generated in VHDL or Verilog - the formats that will work with popular HDL simulation tools. As a matter of fact because of standard IEEE languages, we work with all the leading HDL synthesis and simulation tools. We provide automation scripts that can be tailored and customized to automate the subsequent steps in the flow, for example to kick off a synthesis process with a downstream synthesis tool.

A particular use case we are seeing is customers want to do design space exploration, generate some designs, run that through the synthesis, get some results in terms of clock rates and gate counts and then if it is not meeting the requirements they can go back and quickly iterate. They can run multiple designs in a very short period of time. One way we support that is providing a choice of hardware implementations for the various block supported in the product. If you have a vector multiplication or filter, we have parallel implementations, serial implementations and sometimes in between clock gated or pipelined implementation. In a sense by selecting these, you can turn the knob a bit
between the high speed versus more area versus a little bit more latency and slower speed versus small with regard to area. When you do that design space exploration, the specification of those choices is maintained in a separate control file which can be associated with the model. You can save that and reuse it.

We also handle existing or legacy or externally developed HDL. This is handled through a black box import mechanism that defines the interfaces so that the HDL does not touch the internal workings of it. You can bring that in through Link for ModelSim block. It can be co-simulated with the rest of the design and verified in the system context. When we generate the HDL code for the blocks supported with this product, we also generate the interface code for any of these co-simulation blocks so that at the implementation the legacy code can be included.

Finally the code contains comments that indicate which part of the model generated the code. You can trace back from the implemented HDL back to the source model. That supports debugging and dealing with questions that might arise during the development.

The 80 Simulink blocks. How does that map into the world of possibilities? Can this product synthesize virtually any product under the sun?

Any product under the sun is an unrealistic expectation for a version one product. We did an extensive beta test and gathered requirements from our customers. They are in a variety of industries. They tend to be doing signal processing intensive type of applications such as wireless communications, some multimedia, some video processing. There are also some feedback control types of applications. We have asked those customers that we have been working with what kind of building blocks they use to build their IP in those applications and prioritized them in that way. They tend to be fundamental blocks going from an adder or delay element or a flip flop up to things like filters. There
are certainly more complex algorithms that can be designed in hardware. But we have had feedback from customers that although they would like that in the future and that would make some tasks easier, they typically build up their own IP out of lower level elements for those types of applications. It is really their kind of secret sauce. We think there is a good range of applications. It is not everything under the sun. There will be a steadily expanding set of blocks in terms of scope and greater complexity pf algorithms over time. We think we have laid the foundation so that a pretty broad range can be supported.

If most but not all of a design is covered by these 80 blocks, how do they get synthesizable code for the entire design?

First of all if they have an existing design or something they are developing, the tool will give them a report. There is essentially a compatibility checker that will tell them if they have any blocks that are not supported. If a complex algorithmic block is not supported, one approach is that they can sometimes break it down into smaller components and construct an equivalent block out of blocks that are supported. The other approach is that they could potentially hand code that portion and bring that in through the black box mechanism and include it that way. These are the ways they can work around the limitations.

Simulink has links to ModelSim. You said the product works with a variety of simulators and synthesis tools. Is the link to ModelSim more than a marketing relationship? Is there some advantage to using ModelSim?

There are two aspects to it. The black box import and co-simulation style of verification is supported only with ModelSim today. There are obviously other popular HDL simulators that would make sense to do in the future. In terms of exporting the testbench and having the code work with any HDL simulator is independent. Another style is co-simulation style where you are using the model as the testbench for the generated code. That's one mechanism. Many customers may be using this tool to generate components or subsystems but not the entire design at least initially. They mean to integrate that with other code derived from other means, typically hand coded. In that environment because
out code is completely compatible and works with those simulation tools: Mentor, Cadence, Synopsis.

Would you describe the workflow with and without this new product?

Although things are beginning to change and in many ways have changed in embedded software design flows in a number of markets. In terms of hardware design there is typically a divide between system algorithm designers and hardware designers who implement in ASICs and FPGAs. The system designers typically convert the algorithms, they test them, they make sure they are working functionally correct and create a design document. The design documents get thrown over the wall to the hardware designers who need to implement them. They have to interpret this and hand code the HDL and also hand code the testbench which can be an order of magnitude more code than the actual code going into the

Another challenge with this traditional process is that typically the components are simulated separately. The overall chip design is divided up into teams. Three engineers here and there could be a dozen or more there each doing their own part, doing component level testing. They can not really do system level testing until they gather a full prototype chip in place which is pretty late in the process. Another issue is that the specification is typically maintained separately from the design. Sometimes the specification is not updated at all.

With Simulink HDL Coder and model based design we have one environment for the system, software and hardware; a totally executable specification that can be refined as the actual basis for the design and can be maintained. There is a sense of one truth, one reference that evolves and that gets elaborated throughout the process unlike paper documents. When you do that, you can apply certain system level metrics to determine whether the implementation has degraded the design in any way from the specification.

The elaboration takes you from an idealized floating point model with idealized timing to something that is bit exact and cycle accurate to how the hardware is intended to work. Design space exploration where you can control the options and reuse them. Overall this design methodology promotes IP reuse access projects and technologies. If you want to switch vendors or go from and FPGA to an ASIC or even take functionality that used to run on a DSP and put it into hardware you can do that without completely going back to the drawing board.

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-- Jack Horgan, EDACafe.com Contributing Editor.

Review Article
  • October 09, 2008
    Reviewed by 'Mike'
    Hello Jack:
    I read your articles and I appreciate the depth to which you probe the various subjects you cover. In your recent article in which you interviewed Ken Karnosfky, Director of Signal Processing and Communication at MathWorks, I believe you missed uncovering HDL Coder's (HDLC) most significant competition which I think your readers would benefit knowing about.
    I should mention I am a sales manager for Synplicity, and my geographical responsibility is the central US. Synplicity has a product in the exact space as HDLC, called Synplify-DSP. It interfaces to Simulink and it outputs vendor and technology independent, synthesizable RTL. It has been on the market for 2 years and is doing well. EDACafe carried the tool's introductory announcement (http://www10.edacafe.com/nbc/articles/view_article.php?section=CorpNews&articleid=123486) which included a quotation from Ken Karnosfky in support -see next paragraph below.
    "DSP designers are increasingly targeting FPGAs for implementation of high-performance DSP designs," said Ken Karnofsky, marketing director for DSP and communications products at The MathWorks. "Synplicity has delivered sophisticated tools for users to generate high-quality RTL code from Simulink that not only delivers impressive QoR, but leverages the comprehensive DSP simulation and analysis already built into Simulink."
    Synplify-DSP is the only tool offering true synthesis of the Simulink model (automatic folding, pipelining, multi-channelization, polyphase decomposition) and we uniquely offer technology specific RTL output, which is optimized for high quality of results and can be retargeted with the push of a button. We have several public success stories to date (http://www.synplicity.com/literature/success/pdf/ss_ssg06.pdf for one). The tool has come a long way since it's introduction and we continue to improve the tool with each release, recently adding M-code control logic description support, vector support, and RTL import support for example. A simple Google of Synplify-DSP will yield many related, informative links if you are interested.
    I know the focus of your article was HDLC and it is good to raise awareness for this tool specifically, and DSP development flows in general. There are several options for the designer to consider and Synplify-DSP is certainly one of them.
    Thanks for listening. I'll keep reading.
    Mike Lux
    Central Area Sales Director

      5 of 7 found this review helpful.
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