October 02, 2006
MathWorks: Simulink HDL Coder
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What are the key features of Simulink HDL Coder?
It synthesizes both the HDL and Verilog. There are about 80 Simulink blocks for data path in V1.0. Control logic is handled by the Mealy and Moore state machines that are modeled in the Stateflow product. These are the typical finite state machines elements that are used in hardware implementations. The code is technology independent, device independent, bit exact and cycle accurate implementation of the model.
In addition to synthesizable code we also generate the HDL testbench. The engineer has already created the testbench in the model and that testbench can be generated in VHDL or Verilog - the formats that will work with popular HDL simulation tools. As a matter of fact because of standard IEEE languages, we work with all the leading HDL synthesis and simulation tools. We provide automation scripts that can be tailored and customized to automate the subsequent steps in the flow, for example to kick off a synthesis process with a downstream synthesis tool.
between the high speed versus more area versus a little bit more latency and slower speed versus small with regard to area. When you do that design space exploration, the specification of those choices is maintained in a separate control file which can be associated with the model. You can save that and reuse it.
We also handle existing or legacy or externally developed HDL. This is handled through a black box import mechanism that defines the interfaces so that the HDL does not touch the internal workings of it. You can bring that in through Link for ModelSim block. It can be co-simulated with the rest of the design and verified in the system context. When we generate the HDL code for the blocks supported with this product, we also generate the interface code for any of these co-simulation blocks so that at the implementation the legacy code can be included.
Finally the code contains comments that indicate which part of the model generated the code. You can trace back from the implemented HDL back to the source model. That supports debugging and dealing with questions that might arise during the development.
The 80 Simulink blocks. How does that map into the world of possibilities? Can this product synthesize virtually any product under the sun?
are certainly more complex algorithms that can be designed in hardware. But we have had feedback from customers that although they would like that in the future and that would make some tasks easier, they typically build up their own IP out of lower level elements for those types of applications. It is really their kind of secret sauce. We think there is a good range of applications. It is not everything under the sun. There will be a steadily expanding set of blocks in terms of scope and greater complexity pf algorithms over time. We think we have laid the foundation so that a pretty broad range can be supported.
If most but not all of a design is covered by these 80 blocks, how do they get synthesizable code for the entire design?
First of all if they have an existing design or something they are developing, the tool will give them a report. There is essentially a compatibility checker that will tell them if they have any blocks that are not supported. If a complex algorithmic block is not supported, one approach is that they can sometimes break it down into smaller components and construct an equivalent block out of blocks that are supported. The other approach is that they could potentially hand code that portion and bring that in through the black box mechanism and include it that way. These are the ways they can work around the limitations.
Simulink has links to ModelSim. You said the product works with a variety of simulators and synthesis tools. Is the link to ModelSim more than a marketing relationship? Is there some advantage to using ModelSim?
out code is completely compatible and works with those simulation tools: Mentor, Cadence, Synopsis.
Would you describe the workflow with and without this new product?
Another challenge with this traditional process is that typically the components are simulated separately. The overall chip design is divided up into teams. Three engineers here and there could be a dozen or more there each doing their own part, doing component level testing. They can not really do system level testing until they gather a full prototype chip in place which is pretty late in the process. Another issue is that the specification is typically maintained separately from the design. Sometimes the specification is not updated at all.
With Simulink HDL Coder and model based design we have one environment for the system, software and hardware; a totally executable specification that can be refined as the actual basis for the design and can be maintained. There is a sense of one truth, one reference that evolves and that gets elaborated throughout the process unlike paper documents. When you do that, you can apply certain system level metrics to determine whether the implementation has degraded the design in any way from the specification.
The elaboration takes you from an idealized floating point model with idealized timing to something that is bit exact and cycle accurate to how the hardware is intended to work. Design space exploration where you can control the options and reuse them. Overall this design methodology promotes IP reuse access projects and technologies. If you want to switch vendors or go from and FPGA to an ASIC or even take functionality that used to run on a DSP and put it into hardware you can do that without completely going back to the drawing board.
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-- Jack Horgan, EDACafe.com Contributing Editor.