September 18, 2006
Synopsys & SystemVerilog Verification Methodology Manual (VMM)
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Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

You tend to find a wide variety of where design teams are in that process. You find there are some design teams that have no legacy. They are really fresh. They are a new team beginning a new project. They really don't need any stuff developed in the past. They have the luxury of picking whatever is best. The vast majority of companies and design teams are going SystemVerilog because they see that's the obvious path. A little more complicated situation is where a project is doing a new version of a design with a legacy testbench. Many times there are thousands of lines of code. The verification or design team doesn't want to throw it away. In our testbench environment we can handle
Verilog, VHLD or C kinds of testbenches at the same time. We see a lot of designs teams that were VHDL based where they see the future of SystemVerilog. They have some verification IP models in HDL. Our VCS + NTV products will support running not only all the SystemVerilog but also run their VHDL, Verilog or C code. It is really important to be able to support that legacy and at the same time give them the industry standard new language and the performance they would like to get out of it.

What about the donation to Accellera?

Editor: Accellera was formed in 2000 through the unification of Open Verilog International and VHDL International to focus on identifying new standards, development of standards and formats, and to foster the adoption of new methodologies. Over the years, Accellera has developed eight standards that have been ratified by the IEEE. Accellera's recent successes in advanced design and verification language standards include SystemVerilog and the Property Specification Language (PSL)

We've donated our assertion library to Accellera. I don't know how familiar you are with checker or assertion library concept. A lot of teams will write assertions from scratch using a language like SVA (SystemVerilog Assertions). What is really handy is to be able to have a library of checkers at a high level kind of like macros where you can instantiate a checker to check a particular common kind of condition. Those sort of things are usually built up in the form of a library. To date many different technology suppliers like Synopsys have had their own library of checkers. We wanted to further the broad adoption of SystemVerilog. Based upon feedback from our customers, we took our
assertion library and donated it to Accellera.

There is a current library called OVL (Open Verilog Library). The OVL library is totally portable and is used across anybody's simulation platform. That's sort of the common denominator today in assertion libraries. We've donated assertions to Accellera. It will be up to Accellera to decide how they want to deliver those assertions. They will have the option of being able to create an extension to the current OVL library or perhaps a new library. Whatever they decide to do, the important point is that there is a richer set of library constructs that design teams can pick from. And being that these are Accellera endorsed and delivered standard libraries, they would likely be portable
across anybody's tools.

What was Synopsys' motivation for this generous donation?

We do two types of things. We do things that make life better for our customers which may or may not directly help us. There are things that we do that are really in the spirit of helping our customers without regard for ourselves. Then there are things that we do to maximize our opportunity within the marketplace. Things like identifying industry standards and donating technology. We do this all the time. We do that because that's what our users believe is very important to have. If we contribute that donation, we make their lives better. We believe our unique advantage is in how well we execute around those donations. The fact that we would help create the SystemVerilog language as an industry standard that helps all of our customers but it also helps all of our competitors to build to a standard language. Our advantage we believe is that we can come back and say now that you have chosen to go down the path of an industry standard language or use an industry standard library like these extensions to OVL, our implementation is better than anybody else. Ours is faster, more robust, better integrated. Ours is supported by verification IP. We don't think that proprietary languages, proprietary APIs, proprietary environments are the way to go. Users don't like that. It is not in their best interest. We appeal to our end users by helping them get to the point
where they can use really good standard techno logy. Then they can pick and choose what is the very best implementation of that. We are confident that we have that.

Is there anything on the product front for SystemVerilog coming up for Synopsys?

The most recent announcement was providing SystemVerilog across the full flow with Design Compiler, Formality as well as our verification platform. We are always doing more things. There will certainly be more technology, more in the way of product technology, more in the way of verification IP, more in the way of methodology to come in the near future. We will have to get back to you when we are ready to talk to you about those things.

The top articles over the last two weeks as determined by the number of readers were:

Cadence Reinvents Virtuoso Platform for New Generations of Complex Custom IC Designs The new Virtuoso platform was beta-tested with a number of semiconductor and fabless design companies, including Avago Technologies, Infineon Technologies, National Semiconductor Corporation, PMC-Sierra, QUALCOMM, and Renesas Technology. The Virtuoso platform introduces an automated constraint-driven methodology to custom design, helping design teams maintain design intent throughout the entire design flow. The platform automates the communication and application of complex design constraints from
specification through layout to verification. In addition, the Virtuoso platform is built on OpenAccess. To better meet diverse customer needs for design software, the Virtuoso platform is available in tiered configurations, Virtuoso L, XL, and GXL, which provide multiple levels of technology tailored to specific levels of design complexity.

Cadence Removes Design Team Barriers for Broad Deployment of Hardware Assisted Verification Cadence announced the introduction of Cadence® Incisive® Design Team Xtreme III systems, the next generation of the Incisive Xtreme series of accelerator/emulators within the Incisive functional verification platform. Xtreme III, the highest density (volume per gates) acceleration/emulation system, offers twice the performance of Xtreme Server with 10-100,000 times the simulation performance gain, supporting up to 72M gates in a single chassis. Xtreme III systems are offered in two tiers:
Xtreme III Desktop, an entry level product that supports simulation, acceleration and targetless emulation, and Xtreme III System that also offers in-circuit emulation capabilities. Both systems can accommodate up to 12 users simultaneously making them the premier acceleration/emulation offering for the entire design team.

Mentor Graphics Announces the Latest Release of Its Board Station Printed Circuit Board Design Flow The Board Station flow includes tools for design creation, layout and manufacture, and is designed to meet the requirements of enterprise design teams. This release offers improved integration with the enterprise, as well as improved design productivity and 'what if' signal integrity (SI) analysis.

Solido Design Automation Announces Private Investment by Technology Heavyweights; Technology and Algorithms New to EDA Industry Attract Non-Traditional Investors Private investors include Jim Rutt (formerly CEO of Network Solutions Inc.), Doyne Farmer (McKinsey Professor, Sante Fe, Institute, and the co-founder and former co-president of Prediction Company), John Koza (a consulting professor in the department of electrical engineering, School of Engineering, at Stanford University.) , Martin Keane (consultant to various computer-related and gaming-related companies) and Matthew Ragget
(managing partner of ADAUS Ventures Inc. He has served as president and CEO of Analog Design Automation). Solido Design pioneers transistor-level design enhancements solutions for analog/mixed-signal design, as well as custom digital and memory design, for the EDA market.

EVE Names Joseph Rothman Senior Vice President of Business Development; Position Created to Manage Vendor Partner Relations, Major Accounts Rothman will be based in EVE's U.S. headquarters located in San Jose, Calif. He will be responsible for managing partnerships with embedded processor companies and relationships with EVE's major accounts. In 1992, Rothman founded and served as chief executive officer of CARDtools Systems, one of the first electronic system level (ESL) companies. Most recently, he held the position of
senior vice president of US Business Operations at ProDesign. Earlier in his career, he worked at Ready Systems, Hewlett Packard and GE in product and marketing management positions.

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-- Jack Horgan, Contributing Editor.


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