September 18, 2006
Synopsys & SystemVerilog Verification Methodology Manual (VMM)
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Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
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Over recent months Synopsys has issued several press releases about their support for SystemVerilog. On March 20th they announced support for the SystemVerilog language throughout its suite of design and verification products. On the same day they announced introduced SystemVerilog verification IP support for its VCS Verification Library and a new native SystemVerilog parser in their Formality equivalence checker. On July 26 the firm announced that it has donated a library of advanced SystemVerilog assertion checkers defined in the ARM-Synopsys Verification Methodology Manual (VMM) for SystemVerilog to Accellera. Recently, I had an opportunity to discuss these with George Zafiropoulos, VP of Marketing Synopsys Verification Group

Would you provide us with a brief biography?
I have been here at Synopsys since the middle of last year, just about one year. My role here at Synopsys is VP of Marketing for the verification business. Prior to that I spent about 9 years running verification platform marketing at Cadence and at Quickturn Design Systems before they were acquired by Cadence. Before that I was at this little startup company called Synopsys from 1989 to 1996 also in marketing. Before that I was at other EDA companies. I have been in the EDA business far too long, for 20 something years, in verification for most of that time.

What do you see as the purpose of Marketing, as your role at Synopsys?
A lot of our role is to help to understand what the customers' requirements are and where the industry is going from a strategic point of view, to help the company understand what our customers' needs are, and to make sure we can meet those needs. Also to help communicate to our customers and potential customers about the value of what we have to offer.

How do you accomplish that?
In understanding customers' needs I think it is spending time with our users and customers to understand what their challenges are, understand what is working well in their current verification environment and where they can use some help. Sometimes that help turns out to be education and knowledge, sometimes it is methodology, sometimes IP and sometimes it is technology in the form of software applications to help them do a better job in verification. So really, it's spending a lot of time with users is the biggest source of information.

In terms of communicating what we've got is a traditional communication challenge - articles, publications, trade shows and so forth. Increasingly publications are becoming a major component of that. We spend a lot of time in one-on-one with our customers. So while we try to understand what their issues are, we are also educating them on what we have to offer.

How was the Design Automation Conference for you this year?
Overall DAC was quite good for us. I spent my time talking with customers about verification related things. Verification is a pretty hot topic. There was a lot of interest. We sponsored a luncheon event about System Verilog. We had a great set of panelists from several of our users. They talked about the current state of adoption of SystemVerilog and they are using that and the impact of that. That was really good. We had a very big turn out at this event. We also sponsored a breakfast for the Accellera standard organization. A lot of that was discussion around SystemVerilog adoption. That was a sellout.

What were the recent press releases all about?
The first press release on July 18th was about the momentum for our methodology. The second was on July 26th about a donation we've made of SystemVerilog Assertion Libraries to Accellera.

The top story is industry momentum is building about the methodology that we've developed between Synopsys and ARM for the deployment of verification methodology for SystemVerilog based designs. The point is that we've seen substantial interest in the methodology we've developed. The supporting proof points for that are: We've got several endorsements. We've seen a big demand for the publication that we've jointly put out which is the Verification Methodology Manual (VMM) for SystemVerilog. We've got lots of users downloading our library that supports the VMM. And we've seen a growing ecosystem around publications and training courses being offered in support of our methodology.

How much does the book cost?
$129. If you want to but it on Amazon, you can get it for less than that. In the spirit of full disclosure, they sent me a book for free. The plot is familiar but character development is weak.

What were the user endorsements?
As part of the press release we identified there companies which were publicly acknowledging the verification methodology: AMR, Vitesse and Alacritech. ARM of course being a co-author of the publication you would expect that they would endorse it. Keith Clark, who ran a lot of the processor development for ARM, is a key senior guy in the ARM organization. He says “The VMM methodology is being followed with great success by many companies in the electronic design industry. A keen interest for ARM is to make sure that their designers designing in ARM technology to their silicon have a solid methodology for doing design and verification because that is becoming a really big headache. They are a pretty big proponent of SystemVerilog because they see that as having one industry standard language for design and verification as a really good thing. They have been a big proponent of working closely with us for a number of years now on the standardization of SystemVerilog.

Clearly the book was not written over a weekend. What was the motivation that sparked the effort and what was the size of that effort?
The methodology you see in VMM is a combination of a lot of guys with a lot of verification project experience. Combination of things. One element that is set into this is that we developed a methodology called RVM. RVM has been deployed by a lot of our customers primarily in the Vera testbench language. One of the key co-authors of the book is Janick Bergeron. Janick was one of the principals of a company called Qualis whose primary consulting business was verification. Janick was personally involved with many, many companies doing advanced verification. Synopsys acquired Qualis (April 2003). That brought in a lot of additional verification expertise. That was a big contribution to the development of the methodology. Thirdly, working with ARM. They have a lot of verification expertise working around not just verifying their cores but having to support so many customers doing designs that are based upon ARM that they felt that having a standardized verification methodology that was well understood and well documented and well supported by the technology would really streamline their customers, our joint customers, ability to get designs done. The VMM was developed over the course of a year, a year and a half as we developed into a publication that came out as VMM. The ground work for that has been accumulating for several years in experiences at Synopsys, Qualis and ARM.

What does RVM stand for?
Reuse Verification Methodology. RVM has been deployed by numerous customers over the years but not around SystemVerilog per se. It was really more around Vera. I am sure that you know that SystemVerilog testbench a lot of that technology was original donation from Synopsys from Vera. So it was a very natural extension.

There are a couple of other endorsements from Vitesse and Alacritech with very similar points of view from users of the methodology. There are two other public endorsements that were not part of the press release. Ross Video adopted our VCS NTV technology. NTV native testbench which means the testbench compiles and runs natively in the simulation kernel which gives high performance. Ross adopted our technology for its performance capability and because of the VMM methodology. Similarly form S3 (Silicon Software Systems) also using VCS & NTV deploying it in a verification methodology as prescribed in the book.

We originally released the first edition of VMM in September of last year. Today over 3,500 copies have been sold which is quite good. According to Carl Harris the Springer editor on the VMM book this is one of the fastest selling EDA books. Maybe by NY Times best seller list standards, 3500 copies don't sound like that many but in EDA it is pretty big, so much so that we decided to produce a Japanese version. That was published in February. The Japanese version of VMM while it is based on the English version we also worked with about a dozen Japanese companies, electronic design companies, consulting companies and others as well as the STARC organization. The reason for that is to collaborate with a lot of our end users to make sure that they understood and could comment on this version of VMM, We are looking at what other languages might be appropriate.

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-- Jack Horgan, Contributing Editor.


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