August 07, 2006
TSMC's Reference Flow 7.0 and DFM Initiative
Please note that contributed articles, blog entries, and comments posted on are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


Perhaps the biggest beneficiary of TSMC's Reference Flow 7.0 is Magma who was added as a third implementation track. Clearly Magma thinks so. During DAC I attended a “free” dinner hosted by Magma. Prior to the meal Magma and TSMC gave presentations. So much for the “free” dinner. During his presentation Rajeev Madhavan, Magma Chairman and CEO, said
“We worked with TSMC for a long time. Achieving this Reference Flow for Magma is a major, major significant achievement. For the last few years we have had customers talk about that we are not in the TSMZC reference flow and that you are not compliant with TSMC. Even though Magma has a lot of customers, this was a major stumbling clock. .. I really want to thank TSMC for the excellent support they provided us in making this happen.”
TSMC is not the only foundry with reference flows. For example from UMC (United Microelectronics Corporation) website we have:
Given the deep sub-micron design challenges that circuit designers are facing, UMC Reference Design Flows provide customers with silicon-proven design methodologies that reduce time-to-market by enabling manufacturability. The UMC Reference Design Flows incorporate 3rd-party EDA vendor's baseline design flows to address issues such as timing closure, signal integrity, leakage power and design for manufacturability and adopt a hierarchical design approach built upon silicon validated process libraries. The UMC Reference Design Flows cover from schematic/RTL coding all the way to GDS-II generation and support Cadence, Magma, Mentor and Synopsys EDA tools. All of these tools have been
correlated to UMC silicon and can be interchanged for added flexibility.
Chartered Semiconductor Manufacturing also has reference flows with Cadence, Synopsys and Magma. ARM has the ARM Implementation Reference Methodology.

The top articles over the last two weeks as determined by the number of readers were:

More than 11,000 Attend 43rd Design Automation Conference for Highest Turnout in Five Years Preliminary DAC attendance numbers broken out by category are: 3,231 registered conference attendees; 3,421 registered exhibit attendees and 4,700 total exhibitors, visitors and guests.

Agilent Technologies Signs Agreement to Acquire Xpedion Design Systems, a Leading Provider of RFIC Simulation and Verification Software Agilent Technologies and Xpedion Design Systems, Inc. announced they have signed a definitive agreement for Agilent to acquire Xpedion, a privately held company that provides software for wireless and high-speed digital circuit and systems design in the communications industry. The transaction is subject to standard closing conditions. Financial details were not disclosed. Xpedion's GoldenGate product enables RFIC designers to analyze their designs at the
transistor level faster and more accurately.

Pinebush Technologies Expands EDA Product Lines Pinebush Technologies, Inc., a leader in printing and plotting software, has expanded its EDA product lines with the introduction of HyperStudio, a suite of viewing, transformation, printing, and plotting tools for the physical design engineer.

Cadence Reports Q2 Revenue Up 12% Over Q2 2005 Cadence reported second quarter 2006 revenue of $359 million, an increase of 12 percent over the $321 million reported for the same period in 2005. On a GAAP basis, Cadence recognized net income of $30 million, or $0.10 per share on a diluted basis, in the second quarter of 2006, compared to $0.5 million, or $0.00 per share on a diluted basis, in the same period in 2005.

Intel Unveils World's Best Processor; New Product Line Delivers Record Breaking Performance While Consuming Less Power Intel unveiled 10 Intel Core 2 Duo and Intel Core 2 Extreme processors for consumer and business desktop and laptop PCs and workstations. The desktop PC version of the processors also provide up to a 40 percent increase in performance and are more than 40 percent more energy efficient versus Intel's previous best processor. The Intel Core 2 Duo processor family consists of five desktop PC processors tailored for business, home, and enthusiast users, such as high-end gamers,
and five mobile PC processors designed to fit the needs of a mobile lifestyle

STARC Adds Magma's Quartz SSTA Statistical Analysis and Optimization Solution to Variation-Aware 65- and 45-nm Design Methodology Magma announced that the Semiconductor Technology Academic Research Center (STARC) of Japan has chosen Magma's Quartz SSTA statistical static timing analysis and optimization software for its process-friendly design flow methodology project for 65- and 45- nm and smaller geometries. Quartz SSTA is part of the variation-aware design methodology that's currently under development and slated for early 2007 release.

Other EDA News

Other IP & SoC News

« Previous Page 1 | 2 | 3 | 4 | 5  Next Page »

You can find the full EDACafe event calendar here.

To read more news, click here.

-- Jack Horgan, Contributing Editor.


Review Article Be the first to review this article
Featured Video
More Editorial  
Test Development Engineer(Job Number: 17001697) for Global Foundaries at Santa Clara, CA
Lead Java Platform Engineer IOT-WEB for EDA Careers at San Francisco Area, CA
ASIC Design Engineer 2 for Ambarella at Santa Clara, CA
Technical Support Engineer for EDA Careers at Freemont, CA
Technical Support Engineer Germany/UK for EDA Careers at San Jose, CA
ASIC Design Engineer for Ambarella at Santa Clara, CA
Upcoming Events
CDNLive Silicon Valley 2017 at Santa Clara Convention Center Santa Clara CA - Apr 11 - 12, 2017
10th Anniversary of Cyber-Physical Systems Week at Pittsburgh, PA, USA PA - Apr 18 - 21, 2017
DVCon 2017 China, April 19, 2017, Parkyard Hotel Shanghai, China at Parkyard Hotel Shanghai Shanghai China - Apr 19, 2017
Zuken Innovation World 2017 at Hilton Head Marriott Resort & Spa Hilton Head Island NC - Apr 24 - 26, 2017
S2C: FPGA Base prototyping- Download white paper

Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy