August 07, 2006
TSMC's Reference Flow 7.0 and DFM Initiative
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Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


Perhaps the biggest beneficiary of TSMC's Reference Flow 7.0 is Magma who was added as a third implementation track. Clearly Magma thinks so. During DAC I attended a “free” dinner hosted by Magma. Prior to the meal Magma and TSMC gave presentations. So much for the “free” dinner. During his presentation Rajeev Madhavan, Magma Chairman and CEO, said
“We worked with TSMC for a long time. Achieving this Reference Flow for Magma is a major, major significant achievement. For the last few years we have had customers talk about that we are not in the TSMZC reference flow and that you are not compliant with TSMC. Even though Magma has a lot of customers, this was a major stumbling clock. .. I really want to thank TSMC for the excellent support they provided us in making this happen.”
TSMC is not the only foundry with reference flows. For example from UMC (United Microelectronics Corporation) website we have:
Given the deep sub-micron design challenges that circuit designers are facing, UMC Reference Design Flows provide customers with silicon-proven design methodologies that reduce time-to-market by enabling manufacturability. The UMC Reference Design Flows incorporate 3rd-party EDA vendor's baseline design flows to address issues such as timing closure, signal integrity, leakage power and design for manufacturability and adopt a hierarchical design approach built upon silicon validated process libraries. The UMC Reference Design Flows cover from schematic/RTL coding all the way to GDS-II generation and support Cadence, Magma, Mentor and Synopsys EDA tools. All of these tools have been
correlated to UMC silicon and can be interchanged for added flexibility.
Chartered Semiconductor Manufacturing also has reference flows with Cadence, Synopsys and Magma. ARM has the ARM Implementation Reference Methodology.

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STARC Adds Magma's Quartz SSTA Statistical Analysis and Optimization Solution to Variation-Aware 65- and 45-nm Design Methodology Magma announced that the Semiconductor Technology Academic Research Center (STARC) of Japan has chosen Magma's Quartz SSTA statistical static timing analysis and optimization software for its process-friendly design flow methodology project for 65- and 45- nm and smaller geometries. Quartz SSTA is part of the variation-aware design methodology that's currently under development and slated for early 2007 release.

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-- Jack Horgan, Contributing Editor.


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