July 17, 2006
Buzz@DAC.2006 v2
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor


by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


The Presidio - For this you need a car, but it's well worth the cost. Drive the whole park-like expanse. It's no longer home to the 6th Army. Instead, it's now home to, among others, George Lucas' new Industrial Magic & Light campus, which is just a gem.


Red's Java House - It's funky and just the excuse you need to walk along the newly resurrected Embarcadero, salvaged from concrete-clad obscurity after the '89 Loma Prieta Earthquake. From Willy Mays Plaza to the Embarcadero Center, it's the single most glamorous urban renewal project in the world. Put on your walking shoes and find out why. You'll know you're in the right location if you come upon the bow and arrow.


Rich Faris, Vice President of Marketing and Business Development at Real Intent - This year, Real Intent will be formally unveiling our new family of formal tools, the EnVision family. Conquest and Ascent, our new formal ABV (assertion-based verification) tools, are joined by existing products, Clock Intent Verification and PureTime, to complete the family. The promise of formal verification is that the time to quality is reduced, and tough bugs that can slip through using a dynamic approach are caught. Significant improvements in EnVision include patented automatic proof construction, a new assertion visualization capability, and a unique guided iterative process. To learn
what the "Assertion Density Paradox" is, please come by see us at DAC.


R.I.P. - There are a number of companies that won't be with us this year, including ReShape, TransEDA, and Ignios. Such news begs the question: Better to have innovated and folded, than never to have innovated at all?


Scott Sandler, President and CEO at Novas Software - I think the 'buzz' at DAC will again be ESL and DFM. In ESL, it's "What is it, who will use it, and what will it do for EDA revenue?" While in DFM, it's “Which of the myriad players has real stuff that users can get value from?"


SIGDA PhD Forum - This is always a lot of fun, and it's happening on Tuesday, July 27th, from 6:30 PM to 8:00 PM in Room 310 at Moscone. You can meet the EDA luminaries of tomorrow, and they can brag on their work - and, no doubt, on their advisors as well. Warning - you will be carded along with the rest of the attendees if you ask for a beer.


SPIRIT Consortium Events at DAC - This from Jayne Scheckla, Marketing Programs Manager for System-level Engineering at Mentor Graphics: On behalf of The SPIRIT Consortium, I would like to encourage you to attend our annual general meeting, behind held in conjunction with DAC on Monday, July 24th, from 6:00 PM to 8PM, at the San Francisco Marriott in Salons 1, 2, and 3. The presentations and discussion of roadmap plans will last an hour, followed by a cocktail, networking, and demonstration hour. Demonstrations will include: ARM's Nizar Romdhane talking about "Multi-stage design-flow integration from SystemC, to RTL, to prototype-board debug configuration using IP-XACT"; Beach Solutions' Colin Tattersall talking about "IP-XACT used to drive IP verification using Beach Solution's EASI-Studio tool"; Denali's Sean Smith talking about "Denali's Blueprint demonstration: SystemRDL and IP-XACT - language synergy for combining IP"; Esterel Technologies' Arnaldo Malavasi talking about "ESL synthesis with Esterel Studio and The SPIRIT Consortium specifications"; Improv Systems' Cary Ussery talking about "Integration and Configuration of The Improv Media Platform Using IP-XACT"; Mentor Graphics' John Wilson talking about "Platform Express: An IP-XACT design environment for system
level design and verification"; Philips Semiconductors' Marino Strik talking about "Creating an efficient derivative design flow using the IP-XACT specification"; Poseidon-Systems' Bill Salefski talking about "Performance Matters: Standards help in analyzing the performance characteristics of an embedded system"; and Synopsys' John Swanson talking about "An Integrated IP-XACT Design and Verification flow with Synopsys' coreAssembler and DesignWare IP." I think it's worth sticking around for all of these folks as long as it's open bar the entire hour!


Srinivas Raghvendra, Senior Director of DFM Solutions at Synopsys - At DAC, expect to see a great deal of emphasis on DFM at 65-nanometer-and-below geometries. Designers at 65 nanometers, and below, need DFM tools that will accelerate time to yield, and it's imperative that those design tools also be manufacturing-aware. Since true DFM spans the entire design-to-silicon flow, Synopsys will be highlighting our comprehensive suite of DFM solutions at DAC and demonstrating how we're bridging the gap between design and manufacturing to address the yield challenges facing the industry.


Stephen Maneatis, CEO at True Circuits - We are a leading provider of analog and mixed-signal IP for the semiconductor, systems, and electronics industries. We've recently announced that our Phase-Locked Loop (PLL) and Delay-Locked Loop (DLL) hard macros are available for TSMC and Chartered 65-nanometer processes, and have been shipping to customers for use in their designs. These high-quality, low-jitter PLL and DLL hard macros are designed by TCI, easily integrated, and fully supported, so customers can reduce both design and silicon risks. The hard macros are pin-programmable, highly process tolerant, reusable, and available in a range of frequencies, multiplication
factors, sizes, and functions to suit a wide variety of standards and chip applications.


SystemC Users Meeting - The North American SystemC users are meeting from 1:30 PM to 6:00 PM on Monday, July 24th, in Room 200 at Moscone Center. But before they do, there's an OSCI meeting to enjoy over lunch …


SystemC / SystemVerilog - You need to know more about SystemC / SystemVerilog interactions, and therefore you'll want to be in Moscone Center, Rooms 200 & 210, on Monday, July 24th, from 11:30 AM to 1:45 PM when Johny Srouji, who is Chair of the IEEE SystemVerilog Working Group and Accellera Technical Chairman, and Stuart Swan, who is Technical Chair of the IEEE SystemC Working Group, address the topic. I believe they will be wearing matching ties as a sign of solidarity across these complex language paradigms.


SystemVerilog Panel - Free breakfast is yours if you come to the Wednesday, July 26th, 7:30 AM to 9:30 AM Accellera panel titled: "Mission Possible III: SystemVerilog in Action!" at the Marriott Hotel, Golden Gate Room A1. The premise of the discussion: SystemVerilog is now recognized as "the most impactful new electronic design automation standard delivered to the engineering community in almost 20 years - a tremendous testament to the co-operation and hard work of a large number of technologists from many major EDA, semiconductor and services companies. SystemVerilog is already widely in use to increase design and verification performance,
productivity and quality with broad vendor support and user adoption gaining momentum." I've been told this panel will be exciting - and I know that's true because ARM's John Goodenough, TI's Somdipta Roy, Sun's Thomas Thatcher, Freescale's Mike Burns, and Intel's Matt Maidment are all fun guys - plus, they're morning people who promise to chase away any cobwebs left over from Tuesday night's Denali excesses. I'll be moderating and you all should plan to join us. Please note, however, it's BYOB in the category of Alka-Seltzer and tomato juice.


Tensilica's Paint-by-Numbers - Kudos to Tensilica for leveraging DAC for the sake of culture. They're raising money at their booth for the San Jose Ballet. If you drop by and participate, you'll help Tensilica in their noble effort. It sounds like fun, and I'm going to try to get there to pitch in. Hope you will, too.


UML at DAC - If you missed it, there was an entire
EDA Weekly posted on June 19th , that was devoted entirely to the topic of UML and ESL, etc., and the tutorial that will be taking place all day Sunday, July 23rd, at the outset of the conference. Please take a moment to read that column, and consider attending this forward-looking, daylong discussion. I sincerely believe you will not regret it.




You can find the full EDACafe event calendar here.


To read more news, click here.



-- Peggy Aycinena, EDACafe.com Contributing Editor.


Rating:
Reviews:
Review Article
  • October 09, 2008
    Reviewed by 'Peter'
    Peggy,
    Nice summary for those who will be there, beautiful expression of why you should be there. Just a single negative note, I am from Silicon Valley and I think that we can honestly say that this part of the world is blessed with two hearts, one that beats in beauty and one that beats in reason. There are incredible sights on both sides of the Bay, as I recently rediscovered Oakland and hiked the hills above San Jose.
    Maybe you should have advised all your readers to come early, stay later and bring the family! From Point Lobos to Point Reyes, well, you get the point...

      Was this review helpful to you?   (Report this review as inappropriate)


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