June 26, 2006
Bluespec - ESL Synthesis
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


Bluespec, Inc. manufactures ESL Synthesis toolsets that significantly accelerate hardware design and modeling & reduce verification costs delivering. At the end of May the company announced Open ESL Synthesis Extensions to SystemC to create a unified environment for modeling, design, and verification. I had an opportunity to speak with Shiv Tasker, Bluespec CEO, and George Harper VP of Marketing about the product and their firm.

Would you give me a brief biography?

Shiv Tasker: 17 years in EDA. I started at Intergraph, Valid, and Cadence. I was at ViewLogic (Sr. Vice President for Worldwide Sales, Consulting Services and Corporate Marketing) for a while just before the merger with Synopsys. Then I stepped out of EDA for about 6 years. After that I became a cofounder of Bluespec. It is more than two years old, three in July.

George Harper: I am mostly a chip guy. This is my first EDA company. I have both designed chips (LSI Logic) and marketed chips (Director of Marketing at Trebia Networks, senior marketing positions at Conexant Systems, formerly Maker Communications, and Shiva Corporation).

There is a famous scene in Godfather III where the Al Pacino character says that every time I try to get out they pull me back in. You were out of EDA for six years. What brought you back?

Pain! I am a masochist. Actually, I had a very successful startup in life sciences. I was thinking about what I would do next. I was introduced to Professor Arvind, the Johnson Professor of Computer Science and Engineering at MIT. He teaches computer architecture and computer science. He said he had some interesting technology. He had founded a company called Sandburst which was a fabless semiconductor company offering a 10G-bit Ethernet router. Sandburst has since been acquired by Broadcom. They were developing this Bluespec technology. In 2003 as a result of telecommunication meltdown the VCs were wondering why they were spending money in developing an EDA tool when it was a
chip company, I said “Let me take at look at it. If it is sufficiently interesting, maybe I will write a business plan and spin it out of Sandburst.” It was really a compelling technology. I went out and raised the money and started Bluespec.

The technology was TRS or Term Rewriting Systems (TRS)?

The Arvind concept was elevating how we express design by raising the abstraction level around concurrency. I felt it was really powerful in terms of addressing complex data path, control logic types of problems which had not been successfully solved. A lot of people tried over a number of years, including if you remember Synopsys. Arvind convinced me. When I first encountered the technology I said that there are a lot of bodies here and I have to wonder if the well is poisoned. He said he was teaching a seminar at MIT. “There are bunch of people from Intel, IBM and TI coming. Why don't you come?” I took the seminar and the labs. I talked to the guys from Intel and TI. I asked them what they thought. Is there something here? The unanimous feedback was yes, there is something compelling here. I also had a very long list of things that needed to be fixed to be a commercial product. That's pretty much where we spent the first year putting in the host language around SystemVerilog, which in 2003 was just coming on line. Accellera was going through its standardization process. We did that for a couple of years. It was obvious to us that there would always be a group of people that were more comfortable with C++. We asked ourselves “How can we take the concepts which are where the value is and apply them in a SystemC
environment?” We spent last year doing that. Now we have both a SystemVerilog environment and a SystemC environment.

Bluespec has raised a couple of rounds of venture capital?

We have done a series A and a series B. I would like to think that we have taken less money than most other EDA companies of our vintage and have gone further in terms of both product delivery and customer satisfaction and having reference customers.

How large a company is Bluespec?

We are around 42 people. We have 18 people in the US and 2 in Europe. The rest of them are in Armenia and India. All of our engineering is done in the US. Armenia and India act as our Q/A as well customer support for our European and India customers.

Any particular reason why Armenia and India?

There is a lot of chip design going on in India right now. Large customers like ST and TI have very large organizations in India that do a lot of chip design. We have to find ways of supporting those customers. We choose Armenia because it is very close to Europe, the cost is pretty low and the quality of people is very high.

When did Bluespec introduce its first product?

Our first product was mid 2005. We actually started getting our first customers by about 2Q 05. With new technology and a different methodology, we had a fairly long sales cycle initially. Even though we started working with people, we didn't close out our first order until 2Q05. Since then we have had very good traction.

How many customers does Bluespec have?
We don't list the customers. Most of our major customers are in wireless, mobile applications. Our big customers are ST, TI, Nokia and Analog Devices.

Are the products in production use at these firms?

Yes. The previous product, the one based on SystemVerilog. The one in the SystemC environment is being rolled out this week.

Who was the target of your first product?

Our first product was more or less an RTL replacement. It's targeted at people who are Verilog and VHDL literate and want to move up the level of abstraction in terms of how they do implementations and are comfortable with learning SystemVerilog. This particular product is targeted at architects and verification people and people who are C++ literate and want to find a way of bridging the gap between architecture and implementation.

Would you describe the product you are announcing?

George: We are adding the same concepts that we have proven out in our SystemVerilog product to people using SystemC. In many ways we are taking a technology that people are using for modeling and making it really viable for hardware design. We've got ESL Synthesis extensions similar in concept to Transaction Level Modeling (TLM) extensions in the SystemC world. They are open, free and out there for people to download. People have been downloading since the announcement. We are doing several things with this announcement in terms of technology and product. I think for the first time in a broad based fashion allowing SystemC to be a single environment for everything from modeling to
verification to design, providing a very clear path that didn't exist before from higher level description into hardware for control logic and what we call complex data path, that is data paths that have tightly intertwined control logic that works with that data path providing a solution that we found consistently in the first projects is able to deliver designs, the writing of designs true to verification in less than half the time.

You mentioned projects. Were there any early releases or beta sites?

These are with people who have used Bluespec SystemVerilog product using the same concepts and the same capabilities in a different syntactical environment. For example, just yesterday we got the results from an evaluation whose conclusion was that it was 5 times faster than what the design would have been in a VHDL environment. If you are familiar with Deepchip there is a letter from a designer at ST who concluded that his first design was done in half the time, that's the design through the verification of the module he worked on. The technology is both proven as well as proven with customers with real results. We are expecting to see
the same results in this SystemC environment.

1 | 2 | 3 | 4  Next Page »

You can find the full EDACafe event calendar here.

To read more news, click here.

-- Jack Horgan, EDACafe.com Contributing Editor.


Review Article Be the first to review this article


Featured Video
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Acquiring Mentor: Four Good Ideas, One Great
More Editorial  
Manager, Field Applications Engineering for Real Intent at Sunnyvale, CA
Upcoming Events
SEMICON Europe at Grenoble France - Oct 25 - 27, 2016
ARM TechCon 2016 at Santa Clara Convention Center Santa Clara CA - Oct 25 - 27, 2016
Call For Proposals Now Open! at Santa Clara Convention Center, Santa Clara, CA California CA - Oct 25 - 27, 2016
DeviceWerx - 2016 at Green Valley Ranch Casino & Resort Las Vegas NV - Nov 3 - 4, 2016
S2C: FPGA Base prototyping- Download white paper

Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy