May 22, 2006
Buzz@DAC.2006
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor


by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


Tom Quan, Vice President of Marketing at Applied Wave Research (AWR) - The general buzz continues around the path to maturity and rate of adoption of sub-100 micron DFM technologies and flow. Also hot - analog/RF tools and IP targeting wireless market. For AWR, DAC will mark the beginning of a new direction and focus, "RF design for the masses," by getting our open RF design platform deployed and adopted for designing next generation RF devices. The concept-to-implementation platform, already adopted by thousands of microwave engineers, and now with almost 100 man-years of additional development, is the industry's first and only high-frequency design platform fully integrated with 5 EM simulators, 4 circuit simulators, and 3 physical verification toolsets.

Tom Sandoval, CEO at Calypto Design Systems - Calypto Design Systems moves ESL design from theory to reality with the SLEC v2.0 sequential equivalence checker, the final element completing a true system-level design methodology. Calypto has introduced many product enhancements to SLEC, including a 100x capacity increase, while attracting several top 10 semiconductor companies to its customer base. Calypto will take part in the DAC special session, "Bridging the System to RTL Verification GAP," plus a luncheon panel, "Lessons from the trenches/real-world ESL project experiences - are the advantages worth the cost and effort?"

Tor Ekenberg, CEO at Manhattan Routing - Manhattan Routing will be showing their Physical Window/Optimization Cockpit (PW/OC) solution at DAC 2006. Based on the semi-automatic analysis and targeted optimization features of the tool suite, MRI has developed an automatic solution for closing timing in multi-mode/multi-corner designs. While this automatic solution cannot replace the manual analysis and optimization effort that PW/OC was designed to address, running the automatic optimization step prior to any manual work allows many more timing violations to be addressed automatically. This automated solution is available now and is shipping as part of the OC package.

Victor Berman, Group Director of Language Standards at Cadence Design Systems - There are two main areas of interest: (1) Integrated approaches to power management for 90 nanometers and smaller geometries: It is no secret that the biggest problem that system integrators are facing is the challenge of low power for mobile and consumer products. The most interesting approaches here will be integrated design and verification systems that span the space from architecture through silicon implementation. (2) Maturation of SystemVerilog and SystemC verification infrastructure: The advanced design and verification gurus have accepted the fact of multi-language environments for executing on complex SoC designs. Look for open standard approaches to providing the verification.

VSIA, FSA and Chipestimate.com are sponsoring an event on Monday, July 24th: “How Many Engineers Does It Take? The Real Issues in IP Integration.” IP integration and verification is only getting more complex, expensive, and risky. IP suppliers, integrators, EDA vendors, and foundries must work together in a streamlined fashion to ensure IP success. But are they? Varying degrees of IP quality coupled with a host of business and technical issues makes IP integration the key challenge in modern SoCs. Don't be left holding the cards with your next chip design. This panel will expose the interrelated and often opposing technical and business issues surrounding IP integration and explore how this fragmented industry can work together. Panelists will include Chip Estimates' Adam Traidman, Open Silicon's Naveed Sherwani, Virage Logic's Jim Ensell, TSMC's Kurt Wolf, and IBM's Raminderpal Singh.

Wayne Wolf, Professor of Electrical Engineering at Princeton & Publicity Chair for CEDA - The IEEE Council for Electronic Design Automation [CEDA] has the opportunity to create the “buzz” at DAC with the continuation of its Distinguished Speaker Series Monday, July 24th. A beer and refreshments reception will be followed by a talk from the yet-to-be-announced winner of this year's IEEE Transactions on CAD Best Paper Award. The author will give an in-depth presentation of their work, offering far more detail than the published paper. This event is open to all and offers the promise of meeting new people, while hearing an interesting talk on a cutting-edge EDA topic.



Editor's Note - Thanks to everyone involved in pulling together this first round of commentary on Buzz@DAC.2006. I'm grateful for your help. And, thanks to Ed Lee at Lee PR for the conversation that led to the idea of doing the survey in the first place.

(Photo of De Young museum from the museum website, http://www.thinker.org.)



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-- Peggy Aycinena, EDACafe.com Contributing Editor.


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