May 22, 2006
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Paul Rowbottom, Senior Marketing Manager at Advantest Technology Solutions -Advantest Technology Solutions will demonstrate its new CertiMAX product. CertiMAX enables "real world" event-based semiconductor validation using a PXI-based environment without imposing any of the traditional limitations of cycle-based test. It revolutionizes the validation environment by allowing the functional verification, debug, and characterization of first silicon without deviating from the design environment. Chip designers can literally take an industry- standard VCD file from a simulation tool and use it as is, on silicon. By allowing the design data to be used directly without requiring vector, timing, or format translation, CertiMAX greatly simplifies the validation process
DRAMATICALLY speeding time to market.
Pratap Reddy, Chairman & CEO at ArchPro Design Automation - Current gate-level simulation does not consider the effect on delay when voltages change, because no model or mechanism exists to account for such changes. At this year's DAC, look for technologies that understand multi-voltage designs and their impact on silicon success.
Randy Smith, RLS Consulting - What's hot at DAC will be DFM, especially the D part. Most of the talk has been on the manufacturing side, but there should be a balance. That's going to be a big part of DAC, plus more and more discussion about open source and Open Access. Users will have many more choices in how to construct their design flows.
Rich Goldman, Vice President of Strategic Market Development at Synopsys - At DAC, the system-level issues will be key, plus developments in IP. We have a panel session on where Dreamworks-based animators will show how they translate their work into a movie. That's going to be very cool!
Robert Hum, VP & General Manager Design Verification & Test Division at Mentor Grapics - The buzz at DAC? It's very simple. The vendor floor will continue to consolidate and the show is going to turn back into a technical paper show. DAC will go back to its roots as a show for technology.
one technology or the other.”
Sandipan Bhanot, President & CEO at Knowlent - The buzz at DAC should be: Will any analog vendors step up and provide the tools to make analog signoff a reality? Analog design has always been a black-magic art. SoC tapeout is being impeded by the analog components - the digital portion of the SoC is ready to go, but waits for the analog/mixed-signal portion to be verified. We need to toss the old analog black magic out, and get analog to catch up with digital design. We need an analog signoff design flow and a formal methodology to go from design entry to post layout verification. It's high time for analog to catch up with digital design.
ready-to-use tools that support functional coverage, SystemVerilog testbench, and verification reuse.
seamless development environment.
Xoomsys' solution is based on its unique distributed processing circuit simulation solution.
SPIRIT Consortium - SPIRIT is having an event at DAC on Monday, July 24th where the member companies will be talking about progress made, and new plans for the future. It will be a very interesting event and the entire EDA community is invited to attend.
Steve Ohr, Gartner/Dataquest - If Christian Heidarson is right, major markets in analog design can solve the problems, although Christian and I may disagree about how easy that may be. The trouble is that everybody uses Spice on full-chip verifications. After that it has to be hand crafted. People are going to be talking about that at DAC.
Steve Schulz, President & CEO at Si2 - This is the year of Open Access adoption! We'll be seeing additional vendor products announced around the standard at DAC. I'm hearing, also that it's more and more about collaboration, and that not just around Si2, but an overall industry trend. At 65 and 45 nanometers, the problems are forcing a more collaborative effort, particularly in developing the design tools!
Sunil Mudinuri, Marketing Manager at Zenasis Technologies - Power will be a big DAC topic, and at 65 nanometers, leakage power is the king of power problems. Designers will take advantage of DAC to find out which vendors have attractive leakage power solutions. The reality is that leakage power must be optimized in the context of the design's timing and area requirements. Furthermore, though 'timing' as an issue was identified a long time ago, it is still a major hurdle for design teams, and some of the emerging solutions are worthy of 'buzz'. Zenasis will be showcasing its recently announced ZenTime optimization products for timing, power and area.
Tets Maniwa, GabeOnEDA & EDA Confidential - Features of analog design are going to become much more important to the overall design. In my personal opinion, we need to back off on SoC design and move to multiple chipsets that are optimized for the process. Assembling designs on one chip is a bad idea - that's got to start changing.
Tom Grebinski, President & CEO at OASIS Tooling - OASIS Tooling has spent the last two years working with the leading developers and users of OASIS, the new data format replacing GDSII. Exhibiting at DAC this year for the first time, the company will demonstrate the broader capabilities of OASIS encountered at this leading edge worldwide implementation including advanced OASIS infrastructure, applications, verification, functionality and OASIS acceleration hardware.
Tom Ferry, Vice President of Marketing at Berkeley Design Automation -Berkeley Design Automation provides circuit analysis tools that improve the design and verification of analog and RF ICs. Our Precision Circuit Analysis (PCA) technology closes the analysis gap between what designers can accurately simulate using traditional tools and what is measured in silicon, by allowing designers to fully characterize designs before tapeout. PLL Noise Analyzer, the company's first product, is based on PCA technology and is the only tool that accurately characterizes PLL noise at the transistor level. Our products have been adopted by more than ten of the world's leading
semiconductor companies and used on designs manufactured from 0.5 micron to 65 nanometers.
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-- Peggy Aycinena, EDACafe.com Contributing Editor.
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