May 22, 2006
Please note that contributed articles, blog entries, and comments posted on are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor

by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Jen Bernier, The Hoffman Agency - The buzz at DAC? I won't be there! (I miss EDA!)

Jim Wiley, Senior Technical Director, Brion Technologies - Brion Technologies says that two design manufacturing technologies that will be hot at DAC are immersion lithography and computational lithography. Both are being used by major IC manufactures to minimize the variability in manufacturing ultra sub wavelength patterns. Computational lithography is used to apply and verify pattern proximity corrections and sub-resolution assist features to full-chip layouts - processes such as SRAF placement, model-based RET/OPC and model-based RET/OPC verification. Extremely accurate lithography process models are calibrated to simulate what will print on the wafer with nanometer
accuracy. Brion will be hosting a Computational Lithography Lunch Seminar at DAC, Tuesday, July 25th.

Joe Daniels, SystemVerilog Documentation Specialist - Verification!

Julie Seymour, Senior Director of Corporate Marketing at eSilicon - eSilicon, a semiconductor company that designs and manufactures custom chips for the world's leading electronics companies, will have a significant presence at DAC, including participation by several executives in various panels: Jim Kupec, COO, will be participating in a panel, “Will the Fabless Business Model Survive?” Prasad Subramaniam, Vice President, Design Technology, will be participating in a panel, “Design Team Collaboration: Tools Challenge or Organization Responsibility.”
Javier DeLaCruz, Engineering Manager, Semiconductor Packaging, will be participating in a panel, “Entering the Hot Zone.” Jayaram Bhasker, Architect, is moderating the panel, “The Xbox 360 Uncloaked: Doing What it Takes to get Chips into High-volume Consumer Electronics.”

Karen Bartelson, Director of Quality and Interoperability at Synposys - There's a lot of buzz at DAC! There's the Interoperability Breakfast on Wednesday morning. The Accellera Breakfast is on Wednesday morning, as well. There's the Accellera Technical Achievement Awards - this is the 3rd year. Of course, there's the "Chips for Dummies" course, the Workshop for Women in EDA, and the SystemVerilog Tutorial. Do you need anything more?

Kaushik Sheth, CEO of Rio Design Automation - You might be able to blame the buzz @ DAC on Rio! That's because Rio Design Automation and other EDA companies are starting to understand that designers need to factor a chip's integration with the rest of the electronic system into their design. While designers don't need to become packaging experts, this understanding is becoming crucial. This new attention of the entire system will be a highlight of this year's DAC and welcome news for companies who have missed market opportunities because they weren't “Package Aware” when they designed their chip.

Ken Karnofsky, Director of Marketing, Signal Processing and Communications at The MathWorks - ESL companies will talk about modeling hardware at higher levels of abstraction. But our customers are using model-based design to solve the real problem facing electronics companies - design flaws introduced at specification aren't detected until late in the process. They are eliminating design flaws and achieving multi-million dollar cost reductions and time-to-market advantages because model-based design ensures that the chip works the first time and eliminates error-prone hand-coding of embedded software. At DAC, The MathWorks will introduce technology that strengthens our
leadership in Model-Based Design, which encompasses embedded and electronics system design and verification, and integrates with downstream tools for implementation.

Kevin Steptoe, Vice President of Marketing & Business Development at Pulsic - Analog, mixed-signal, and custom digital will take center stage at DAC this year as companies have concluded that high-volume IC design is a highly specialized arena where yield, area, and performance are commercial priorities. In high-volume markets, tuning nanometer, full-custom designs to maximize yield and profit has been an iterative and largely manual design effort. As the circuitry in these designs grows - for example NAND-Flash control logic is growing rapidly - physical design automation is becoming the only way to design these chips. Expect to see a new physical design automation tools and
methodologies at DAC.

Lauro Rizzatti, Vice President of Worldwide Marketing & General Manager of EVE-USA - Verification will continue to be a topic of discussion during DAC this year, especially the growing use of next-generation hardware assisted verification platforms for simultaneous hardware and embedded software verification. These fast, reliable machines shorten time to tapeout, improve product quality, eliminate re-spins, and accelerate software development ahead of silicon. These systems are replacing existing emulators bogged down by slow speed and high costs. Older generations of emulators have been relegated to hardware debugging applications and can't be used for the most pressing needs
of a design team: hardware/software integration and embedded software validation. Design processes are combined in a seamless development environment.

Linda Prowse Fosler, Vice President of Marketing at VaST Systems Technology - VaST is sponsoring a panel on ESL design and verification at DAC, giving a tutorial on using virtual system prototyping to design and optimize SoC architecture and parallelize hardware/software development, and unveiling the sixth generation of its embedded software development tool. CEO Alain Labat says, "ESL is coming of age due to growing market need and the pressures for on-time product delivery. Silicon embedded systems have huge software content and market pressures that no longer tolerate serial software development. Real embedded system design solutions that enable high-speed, cycle-accurate
concurrent hardware/software design are a critical part of ESL tools and methodologies and are available now."

Max Lloyd, CEO at ViASIC - There'll be a lot going on at the ViASIC booth at DAC. One of our customers, Triad Semiconductor, will be presenting their via-configurable mixed signal array products, which use ViASIC's ViaMask technology. ViASIC will also be unveiling a new product, as well as releasing a new process-node of the ViaMask standard-metal one-mask library for 90-nanometer technologies. Standard-metal libraries can be used to build structured ASICs or as a fabric for developing rapidly configurable sections of an SOC.

Michel Ligthart, COO at Verific - There's nothing hot at DAC, but that's not important, because DAC is the place for me to see my customers, to interact with academia and other vendors. It's all there and more than enough of a value proposition for the conference. It's not like a car show, where you have to have new products every year!

Mike Gianfagna, President & CEO at Aprio - DFM is hot...or is it? How can anyone wade through all the hype and figure out what's real? Aprio will set the record straight at DAC. Through a series of announcements in early July, we will unveil our roadmap for a comprehensive design-for-manufacturability solution, spanning both manufacturing and design applications. Aprio's approach takes aim at the poor communication that exists today between IC design and manufacturing teams. Through partnerships with key suppliers in the design-to-manufacturing chain, Aprio plans to improve chip predictability, performance and yield with minimal impact to current design and manufacturing
workflows. That's what DFM should be.

Naeem Zafar, President & CEO at Pyxis Technology - There will be a lot of talk about DFM at DAC this year. IC designers will hear about new tools that identify manufacturing and yield problems. Multiple vendors will offer lithography simulation, parametric analysis, and yield analysis that can be incorporated into existing IC design flows. However, existing IC design tools are unable to take full advantage of these model-based capabilities. They do not have the ability to avoid DFM/DFY issues during implementation. New startup, Pyxis Technology, brings IC designers a correct-for-manufacturing environment that optimizes designs for the manufacturing process and improves design
yield while achieving design closure.

Nitin Deo, Vice President of Marketing & Business Development at Ponte Solutions - Ponte Solutions will showcase a yield sensitivity analysis system for nanometer designs. Yield Analyzer is built on the foundation of unified models for mission-critical yield issues for any designer of cell libraries, memories, IP, block-level or chip-level designs. For these designs, design rule checking is not sufficient anymore. In order to identify the trade-offs, the designers need a model-based analysis system with actual fab-correlated models. Ponte's Yield Analyzer, delivers accurate analysis for designers to focus on the right optimization techniques.

Open SystemC Initiative - OSCI is hosting a SystemC Technology Symposium and a North American SystemC Users Group Meeting on Monday, July 24th. You'll hear from industry experts speaking on recent SystemC advancements and using SystemC for doing real world system-level design. Status updates on the technology roadmap, IEEE 1666, and TLM will also be presented. The event is sponsored by Cadence, Celoxica, CoWare, Doulos, ESLX, Forte, Mentor Graphics, and Synopsys.

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-- Peggy Aycinena, Contributing Editor.


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