May 22, 2006
Please note that contributed articles, blog entries, and comments posted on are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor

by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Coby Zelnik, Executive Vice President at Sagantec - The buzz at DAC should be whether we see physical implementation tools that take DFM analysis and make corrections on the mask design. DFM started in the 130-nanometer node by implementing back-end post-design techniques to address physical design, which itself is not lithography- and manufacturing-aware. Now, at 65 and 45 nanometers, DFM must be implemented in the design phase. Many vendors are developing better/faster/design-friendlier litho/yield-analysis products for the design phase. Lacking are flexible and powerful physical design manipulation tools to modify design polygons and optimize them based on such
litho-simulation and yield-analysis technologies. A viable automated DFM methodology cannot be implemented without this crucial ingredient.

Craig Cochran, Vice President of Marketing at Jasper Design Automation - Structured, systematic verification is a huge trend and will be a hot topic at DAC this year. We are seeing much interest in up-front verification test planning combining end-to-end full formal with coverage-driven simulation and formal ABV, targeting the most appropriate technique to different parts of the chip. This structured combination of techniques enables users to ensure correctness where it matters most, while getting high coverage across the rest of the design and greatly improving bug hunting and elimination early in the design process. The benefits are both completeness of verification, where
completeness matters most, as well as overall verification productivity.

Dale Pollek, President & CEO at ChipMD - What's hot at DAC in San Francisco? San Francisco won't be hot, it will be cold. Bring a sweater! Remember what Mark Twain said, "The coldest winter I ever spent was a summer in San Francisco." But really, what's hot at DAC will be a new way of doing things. For example, Monte Carlo and global optimization techniques just won't work any more. There are too many computational problems!

Dan Nenni, Vice President of Sales & Marketing at Predictions Software - You have to know your yield to optimize for yield! Predictions Software and Nannor Technologies have joined together to provide modern semiconductor design's first yield sign-off tool. The integration of EYES yield-analysis software and the Accuma chip-level layout optimization tool facilitates the application of full chip yield optimization techniques with calibrated process manufacturing data. In tens of minutes, process calibrated yield models supplied by the leading foundries can be applied to layout via critical area extraction and analysis. The yield trouble spots are then targeted for optimization
and the resulting yield improvements are calculated.

Dian Yang, Vice President of Product Management & General Manager at Apache Design Solutions - Apache Design Solutions, a leader in dynamic power integrity and SoC noise management will be showcasing its silicon integrity platform for high-performance, low-power SoCs at DAC. Highlights include RedHawk-LP, a full-chip transient, waveform accurate, analysis and optimization solution for power-gated designs. Its ability to run full-chip power-up simulation overnight and analyze the impact of mixed-mode operation on timing is critical for 90- and 65-nanometer designs. For hands-on experience with RedHawk-LP, attend the "Hands-On-Tutorial," on Monday, July 24th. Apache will also
participate in a panel discussion, "Entering the Hot Zone - Can You Handle the Heat and Be Cool?" on Tuesday, July 25th.

John Murphy, CEO at Athena Design Systems - New EDA start-up Athena Design will demonstrate its first commercial product at DAC - a new concurrent routing optimization and analysis system that accelerates the productivity of engineers, tools and computing resources so design teams can reach design closure faster with higher quality of results and lower development costs. The system is unique in its ability to automatically and incrementally “analyze-optimize-fix” on the fly using real wires. This provides the level of accuracy required for designs with 90-nanometer and finer geometries. The system works on a distributed multi-processing platform that easily
integrates into existing EDA design environments.

Don Tuite, Sr. Technology Editor for Analog & Power at Electronic Design - I'm an analog guy. I don't go to DAC. I leave that to Dave Maliniak!

Ellen Sentovich, Chair, 43rd Design Automation Conference - DAC will be buzzing, both on the packed exhibit floor and in the many, diverse technical sessions. It has been eight years since DAC has been to San Francisco and everyone knows this location will boost attendance and excitement, so everyone's coming. The MEGa theme, Multimedia, Entertainment, and Games, is timely, exposes cutting-edge problems, and is downright fun! With pavilion panels on topics like Inside the iPod and PSP, and Dreamworks' Innovation, and with MEGa technical sessions, keynotes, and a booth on the floor with cool demos, attendees will appreciate and be buzzing about DAC's MEGa theme
this year.

Emil Girczyc, President & CEO at Summit Design - ESL and Virtual Platforms (VP) are changing companies' design methods and business models. Most of the focus has been on using VP for early software development. Virtual platforms also enable architectural exploration prior to software development. This allows designers to perform rapid architectural design and performance analysis, including “what-if” hardware/software partitioning on single- or multiple-core platforms before the hardware or software is developed. Summit's Panorama Virtual Platform Development solution provides a smooth transition into SystemC TLM models for the platform development. ESL has become
a powerful marketing and pre-sales tool and a way for companies to achieve early design wins.

George Harper, Vice President of Marketing at Bluespec - DAC will be a momentous occasion for SystemC, the language that provides hardware-oriented constructs for C++ as a class library, because it will have finally come into its own. That's because there will be several developments which address shortcomings and allow SystemC to be a unified environment that can be used for modeling, verification and design. SystemC can move from being just another TLM language to a hardware accurate modeling language with full hardware implementation and architecture support.

Gerhard Angst, CEO at Concept Engineering - Concept Engineering develops and markets innovative visualization and debugging technology for commercial EDA vendors, in-house CAD tool developers, FPGA and IC designers. This year at DAC, Concept will be highlighting Nlview Widgets - a family of visualization engines (Tcl/TK, MFC, Qt, Java, Perl/Tk, wxWidgets) that can be easily integrated into EDA tools, SpiceVision PRO - a customizable debugger for SPICE based designs and GateVision PRO - a customizable debugger for Verilog, LEF/DEF and EDIF based designs. Stop by the Concept Engineering booth and see how they can bring light to your design.

Gloria Nichols, Launch Marketing - This DAC, I am most looking forward to, (1) The Denali party. I am not big on the professional 'disco' band (hint, hint Sanjay...), but I love the EDA musician performances. I went to my first Denali party last year, and it was something to remember. (2) The Dataquest event on Sunday evening, both the prognostications and all the familiar faces. As for technology buzz on the DAC floor, my bets are on DFM, ESL, and leakage power. I unabashedly admit to having clients in those areas, but it is because that is where the action is.

Jack Yao, Founder & President at Sandwork Design - Modeling and analyzing deep-submicron analog behavior have become a very important factor for yield. Fast Spice is gaining ground as full-chip, transistor-level timing simulation becomes necessary. A number of companies are developing fast Spice engines/platforms, producing a looming problem in analyzing large results data files and waveform files, sometimes with thousands of parametric sweeps. The only efficient way to bridge that gap is to use a well-integrated, best-in-class solution that provides easy access to and support for analysis of data from all three areas: simulation, hardware measurement, and system-level

Jeff Jussel, Vice President of Marketing at Celoxica - Celoxica will be demonstrating why Agility Compiler has become the tool of choice for behavioral design and synthesis for SystemC. As a single solution for FPGA design and ASIC/SoC prototyping, early TLM models can be quickly realized in working silicon yielding accurate design metrics and RTL for physical design. Celoxica tools have been used in multiple high-visibility design successes, including leading hybrid engines, "bomb-sniffing" technologies and video/image processing applications. Celoxica will also be demonstrating new hardware and software breakthroughs in accelerated computational engines
bringing supercomputing power to cost-effective commercial applications.

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-- Peggy Aycinena, Contributing Editor.


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