May 15, 2006
PLM and cPDm Update
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Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Mentor Graphics Delivers the Next Generation of Functional Verification; Tools, Methodology and Partners Target Verification Productivity and Efficiency. The announcements include the new Questa 6.2 functional verification platform, the industry's first open-source standards- based Advanced Verification Methodology (AVM), and the Questa Vanguard Program (QVP), an organization of over 25 companies dedicated to helping companies build more effective verification flows.

Sierra Design Automation Starts India Operations -- Continues Aggressive Expansion Plans; Focus on Supporting Growing Customer Base and Product Engineering. Sierra Design has established offices in India to support the growing adoption of its products. Sierra Design Automation Private Limited, a wholly owned subsidiary of Sierra Design Automation, Inc., will be based in Bangalore, India and will be headed by Raja Subramaniam, General Manager, Sierra Design Automation Pvt. Ltd. Mr. Subramaniam joins Sierra after a 9 year stint at Synopsys, most recently handling sales in South Asia and India. He was
instrumental in setting up the Synopsys sales and support operations in India

Mentor Graphics Platform Express is the First Platform-Based Design Solution to Support The SPIRIT Consortium's New Specification. The SPIRIT Consortium's specification uses XML to create a machine-interpretable IP databook that includes design information that software tools then use to automatically configure and integrate an IP block into a design. After several years of development, The SPIRIT Consortium states that specification 1.2 provides a complete platform for IP-based design and verification. Platform Express v3.3.0 takes full advantage of the new specification's verification IP enhancements,
providing a new set of generators that support 0-In(R) Checkerware verification IP as well as PSL and OVL assertions.

Other EDA News
  • Other IP & SoC News

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