April 17, 2006
Formal From Spec to Sign Off - Real Intent
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Jack Horgan - Contributing Editor


by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


Freescale Introduces Industry-First Flash-Based 32-bit Microcontroller Families for Single-Chip Connectivity Freescale introduces two 68K/ColdFire microcontroller product families for industrial control applications ranging from remote data collection and security enhancements to home automation and environmental monitoring. The MCF5223x device family is the first 32-bit microcontroller to deliver a Fast Ethernet Controller, Ethernet PHY and flash memory in a single-chip solution. The MCF5222x device family offers the industry's first 32-bit microcontroller with integrated USB On-The-Go and
flash memory. It allows two USB devices to communicate without a host interface, making it ideal for system-to-system communication applications.


Can the chip design - verification divide be plugged in with some knee jerk band aid type strategies? Opinion: Formal verification does not work well on data paths or on large pieces of control logic. A formal verification tool is most efficient when it is used for controlled surgical strikes on small pieces of most complex control logic like the ones in arbiters and cache coherency checkers. Formal verification should begin in the early stages of design and is not suited at all for chip level verification. Similarly, Random Test Pattern Generation or RTPG can be an invaluable tool in getting
to the corner case bugs in simulation that cannot be imagined by the verification engineer, but is useful only if it is kept targeted or directed towards the functionality where we are wary of the existence of bugs. All designs should be verified in a silicon kind of a situation, whether it is FPGA, hardware accelerated or an emulation solution. At that time, O/S kind of a code that will eventually be what the customer will see of the design must be run on the design to ensure that the design will do fine in the cool looking colorful device that is sold in the market.


EDA Startup Nangate Secures $10M in Venture Capital Nangate Inc., announced that it has raised $10M in series A financing from a consortium of investors, including Vaekstfonden, IVS and SEED Capital. The company employs more than 40 people worldwide, with engineering operations in Copenhagen, Denmark and Moscow, Russia. In addition, the company has established an advanced research division in Porto Alegre, Brazil and sales and support offices in Silicon Valley. Nangate tool suite increases the efficiency of digital CMOS ICs to levels previously only achievable with extensive manual efforts
and very large design teams. Targeting the inherent shortcomings of predefined 'one-size-fits-all' standard cell libraries, Nangate provides a range of library optimization tools and solutions that can effectively optimize power consumption and maximize performance while minimizing chip area.


Cadence Announces Executive and Engineering Fellow Promotions on Back of Strong 2005 Business Performance Bill Porter, who joined Cadence in 1994 as corporate controller and has served as SVP and CFO since 1999, was promoted to executive vice president and chief financial officer. Jim Miller was also promoted to executive vice president, Products and Technologies Organization. Miller manages the global Cadence research and development organization responsible for delivering core (digital, analog, RF, mixed signal) and DFM adjacency products and technologies. Miller joined Cadence in 2004 with
more than 20 years experience in engineering and management.




Other EDA News
























Other IP & SoC News







































« Previous Page 1 | 2 | 3 | 4             


You can find the full EDACafe event calendar here.


To read more news, click here.



-- Jack Horgan, EDACafe.com Contributing Editor.


Rating:


Review Article Be the first to review this article
CST Webinar Series

EMA:

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Retail Therapy: Jump starting Black Friday
Peggy AycinenaIP Showcase
by Peggy Aycinena
REUSE 2016: Addressing the Four Freedoms
More Editorial  
Jobs
Principal Circuit Design Engineer for Rambus at Sunnyvale, CA
FAE FIELD APPLICATIONS SAN DIEGO for EDA Careers at San Diego, CA
Development Engineer-WEB SKILLS +++ for EDA Careers at North Valley, CA
Manager, Field Applications Engineering for Real Intent at Sunnyvale, CA
AE-APPS SUPPORT/TMM for EDA Careers at San Jose-SOCAL-AZ, CA
ACCOUNT MANAGER MUNICH GERMANY EU for EDA Careers at MUNICH, Germany
Upcoming Events
Zuken Innovation World 2017, April 24 - 26, 2017, Hilton Head Marriott Resort & Spa in Hilton Head Island, SC at Hilton Head Marriott Resort & Spa Hilton Head Island NC - Apr 24 - 26, 2017
CST Webinar Series



Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy