April 03, 2006
Optimization - Athena Design Systems
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Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


On March 13th EDA startup Athena Design Systems, Inc. unveiled its strategy for delivering a new class of IC optimization tools to address the costly, acutely painful process of achieving design closure for nanometer-scale chips. The system architecture harnesses the power of multi-processing to deliver concurrent optimization and analysis to “analyze/fix” on the fly and optimize with the real wires of a chip. Technology development has been underway at Athena Design for two years. The company plans to introduce commercial availability of its first products in the second quarter of 2006. Before the company launch I had an opportunity to talk with John Murphy, the CEO,
and Dimitris Fotakis, founder and President.

Would you (Dimitris Fotakis) give me a brief bio?

I started my career in EDA after I got out of the Ph.D. program at the University of Wisconsin-Madison in 1994. I went to National Semiconductor. There I was working in the central CAD department. I wrote from scratch a delay calculation tool. I worked with a group in timing analysis and physical analysis methodology. Then I went to High Level Design System. I worked with George Janiack. I worked on the first extractor in the industry that did ASIC chips. When the company was acquired by Cadence, I joined them. I stayed there for 2 or 3 years. Then I became one of the cofounders of AmmoCore Technology. I left AmmoCore in September 2003 and founded Athena Design Systems.

I noticed that there are several other former Ammocore alumni on the Athena team. What happened to AmmoCore?

AmmoCore went out of business after burning through lots of money. I think that the technology was good, the ideas were good. Maybe the combination of the marketplace conditions in terms of the economy and getting late to market was really the problem.

What was your motivation in founding Athena?

I was thinking of getting out of Ammocore that was trying to do a big thing pretty much to compete in the arena of netlist VDS. It was big system, competing with many players. I decided that definitely one of the technologies that to be right form scratch was multiprocessing technology. It has to be applied on a specific point tool function rather than all over the flow, at least to start with. I believed that I had to focus on as specific area. The next thing that I thought that was very compelling and people ignored was that we have the CPU power to really target more than one analysis function with optimization to make decisions on how to incrementally change the design for the back

Would you (John Murphy) give me a brief bio?

I will do it in reverse chronological order. Prior to Athena I was at Cadence. I was there for 12 years. I held a variety of positions. The last position I had was 2 years as advisor and technical staff to Ray Bingham, the CEO. I also held positions as product line VP and VP Technical Field Operations as well as marketing positions. When I was completing my technical advisory duties with Ray, I was looking around for what to do next. I always had a love for working with new technology. During my entire career I have been focused on place and route as an area of expertise. So finding the Athena opportunity and seeing what Dimitiris' vision was and the customers he was working with
was pretty exciting to get into this company and help bring this new technology to market.

Prior to Cadence I was at Cypress Semiconductor for 3½ years. Before that I was at Silvar-Lisco, when they were the largest EDA company. Prior to that, I was at Texas Instruments as a design engineer and manager.

All those firms are large companies. Quite a change to move to a 14 people startup.

Quite a change form Cadence, I will say that. Actually, I said Cypress. We were in a company that was acquired by Cypress. It was structured as a wholly owned subsidiary. We had our own logo and brands. There were 26 employees in that company when Cypress acquired in 1994. So I had some exposure to small companies and I liked that environment.

What was Ray Bingham really like?

Ray Bingham is a great man. He has a very strong skill set in finance and business. He also has a very strong customer orientation, building relationships between himself, his company and his customers. He is also very demanding, very good at getting a lot of hard work out of people.

Ray taught me a lot. Part of what the technical advisory role is in a company like Cadence is to prepare a technologist to work as an executive and gain a business perspective. It's a temporary role which is what is was for me. I spent 2 years in the role. It helped me to understand the different facets of running accompany. Actually I think it is no different running a small company and running a larger company. It is just a matter of how many resources you have and who does what. Being very thoughtful about how things get staged of course running a small company. I had some MBA training in my educational background. So I understand the differences in running a small company and
running a medium sized company in terms of cash management and those kinds of things.

Would you tell me a little about the company?

We are a venture backed startup company. We are focused on the implementation of big electronic ICs, specifically around the timing closure problem. We are 14 people. We have a global reach with our customers around the world. We are announcing our company on March 13th.

What is the user problem that Athena is focused on?

The problem that we are focused on is that the implementation time and cost is really getting out of hand. This comes from the complexity of the big digital systems being designed these days. The issue is that complex physical effects must be dealt with manually. These issues are signal integrity, noise, and so forth. They have to be dealt with manually by the designers in the timing closure process, causing chips to be late to market. If you look at the percentage of design starts in the various geometries, you see that 90 nm is starting to ramp up. Customers that we are talking to are saying that it is taking about twice as long to do 90 nm as it did to do 130 nm and that they are
using twice as many engineers. So costs are tripling and they are missing their market windows. The goal of this company is top cut that in half.

The challenge to address that is finding a path to design closure. The vision around this is to convert what today is a manual process into an automated process. The vision we had when Dimitris started this company was to harness the power of distributed multiprocessing that we see in Linux clusters. These clusters appeared on the scene a few years ago. Folks are trying to figure out how to get a really high return on investment to achieve the level of parallelism they expect from a distributed multiprocessing environment. For us that means a re-architecture of the EDA infrastructure starting with distributed multiprocessing and architecting a system to work such that we get concurrent
analysis and optimization and that we can do on the fly optimization.

What approach are you taking to address the problem and challenge?

The approach we are talking about is to build a new anchor point in the flow. Why is this needed? It is needed because people are doing optimization today in placement. When they do placement of a big IC and work on optimization for timing, they use estimates on the routing. This is then handed off to the router which performs the creation of the actual wires. The next steps are to go through a signoff flow, a set of tools that are certified by the library process group. If the chip passes those screens, it is ready for manufacturing. What we are finding first of all is that the run times are really long. Second of all, these engineers have to loop around this signoff flow with an optimization loop. Our goal is to essentially collapse that into this anchor tool that is a companion to routing so that we do optimization with the real wires. We also manage the routing process. We take the output from placement and plan the routing. We divide the chip up and perform detailed routing using third party tool through standard format interfaces. Then we analyze and fix on the fly in an incremental fashion. Our system must be incremental so that we can look at one net or a small area of the chip,
perform optimization, reroute a small area and then reanalyze and continue the optimization. But we are doing it in an automatic fashion.

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-- Jack Horgan, EDACafe.com Contributing Editor.


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