March 13, 2006
DATE 2006: Between Gemütlichkeit und Angst
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The panel was a complex one that touched on numerous orthogonal concerns that need to be addressed in order to achieve successful design. Next time, the topic should be scheduled for earlier in the day.
** For those willing to get up early on Wednesday morning (and there were many), the 8:30 AM technical panel, "DFM/DFY Design for Manufacturability and Yield," was a must-attend event.
In the first 45 minutes, spokesmen from IBM and the Technical University of Munich laid out in quick-paced detail, a list of the usual suspects implicated in today's design-for-manufacturing and design-for-yield conundrums - reduced channel lengths, tiny feature sizes that are poorly served by lithography limitations, random and systematic errors, wafer-to-wafer and die-to-die defects, badly articulated corners, etc. Even at 8:30 in the morning, this was a nice mini-tutorial that set the stage for the second half of the session.
In the second 45 minutes, the German EDA company, MunEDA, detailed their WiCKeD tool, followed by a spokesman from Infineon endorsing the tool. Their presentations were interesting, and it was easy to spot a number of certified DFM experts in the audience listening attentively. It was also easy to wonder what those certified experts were thinking about the tool, and the larger DFM and DFY issues mentioned over the course of the session. Above all, it was easy to wonder if the industry will come to a decision anytime soon as to what actually constitutes a complete DFM flow. The 8:30 AM panel, I suspect, was showcasing only one part of that flow.
Nonetheless, I liked these Best-of-Show quotes from the session: "Design and technology together equal yield," and, "Every carelessness at the beginning of the design phase will cost valuable ramp-up time, once that design reaches the manufacturer."
In addition: By Wednesday, mid-day, DATE was in full flow. The Exhibition Hall was packed, people were in over-drive trying to maximize their time at the conference, either through interfacing with potential customers at the booths or by attempting to attend as many panels or sessions as possible over the course of the day. Everybody was rushing here and there.
Luckily, food and espresso machines were ubiquitous at DATE all week long. The Synopsys, Mentor, Cadence, and Magma booths were all espresso-enabled, as were those of many other exhibitors. In addition, booth food everywhere was prolific and delicious. And if activity in the particularly well stocked booths was any indication, the lesson is - where there's food and coffee, the crowds are not far behind.
Additionally, and at the surprisingly early hour of 4 o'clock, there was also beer, wine, punch, pretzels, more finger food and a general joie de vivre across the Exhibition Hall floor, with that energy spilling out into the main lobby of the convention center where additional company booths were located.
The overall "Show Stopper Food and Drink Award" for DATE, however, has to go to Hein and Lisa van der Wildt at the Fenix Design Automation booth. They brought with them to Munich, pounds and pounds of fresh herring on ice, which they actually sliced on the spot into savory bite-sized pieces to serve up to their visitors, along with a bracing shot of schnapps. Excellent and pungent all at the same time, luckily the van der Wildts didn't break out the herring until late afternoon each day. The powerful aroma of fresh-sliced herring is not everybody's cup of espresso.
** The lunchtime keynote on Wednesday was delivered with a distinctly American flair - just the facts, Ma'am - by Texas Instruments' Don Shaver. He spoke for a long, technical hour about TI's roadmap towards an energy-efficient, single-chip 4G wireless solution that would run on a paltry 100mW of power, include advanced RF and digital features in a minimalists 10-million gate design, and be built on low-cost CMOS technology and therefore saddle up with a price tag not to exceed 10 bucks. Oh yeah, and the chip would be defect free the first time, every time, and beat the competition regularly in the time-to-market marathon.
Shaver said developing the TI 4G solution will take about 5 years, and will require tools like Matlab, languages like SystemC, super-duper cell libraries, synthesis tools, and IP blocks, as well as sophisticated electrical models and development platforms that will probably include advanced FPGAs and maybe even a structured ASIC here and there. Shaver said it's all achievable, because "design frameworks are our competency." Per Shaver's description, it sounded like TI intends to add their 4G roadmap into their long list of successful, happy trails.
In addition: I spent the bulk of Wednesday afternoon meeting with companies, both in their Exhibition Hall booths and in the Press Room. Although this exercise can be a tedious one, and overly burdened with ponderous PowerPoint presentations, somehow the conversations at DATE take on a special validity. I learned a lot from my visits with Advantest, ACE, Apache, AWR, Celoxica, CriticalBlue, Dubai Silicon Oasis, IMEC, Magma, Nascentric, OCP-IP, Tenison, and TransEDA, and only wish that there would have been more time to patrol the show floor, and drop in and visit with the many technologists ready and able to engage in informative conversations.
On the flip side, I'm of the opinion that journalists' best time at conferences is spent attending sessions, not meeting with companies to hear about product releases. As important as getting that exposure may be to the companies, the journalists are rarely focused on the conversation in the booth, and are probably not paying full attention even when they look like they're fully engaged.
** At the end of the day on Wednesday, people's spirits were starting to drag. Just downing (yet) another shot of espresso couldn't take the edge off the jet lag that had set in for many at that point in the conference. However, those of us who consider ourselves to be conference warriors are not easily defeated. And it was in that mode, that I lasted through 45 minutes of the 4:30 PM panel on nanotechnology in one of the conference room upstairs in the ICM conference complex.
Interesting stuff, that nanotechnology, and these series of panel presentations were no exception. But quantum dots and negative bias temperature instability are the stuff of late-morning physics lectures, not late-afternoon conference panels as the sky is growing dark outside. When I realized my attention span had reached a length comparable to the distance between dopant atoms in a silicon lattice, I decided to excuse myself from the session and attempt to revive in time for the EDAC industry reception that was starting just 45 minutes later.
In addition: By that time, late Wednesday afternoon, the snow had started to fall again in Munich. The skies were darkening, the temperature was dropping, and the folks from the EDA Consortium had just the right antidote. The event they hosted for consortium members at the conference center was great, full of wonderful food and beverages, and lots of good friends enjoying the ambience and the fact that most of their obligations for the week were nearly fulfilled, whether that was presenting keynotes, appearing on, or moderating panels, interfacing with customers, or just getting to Munich at all in the face of the rather epic weather conditions.
** First thing Thursday morning, there was another "early riser" special - a panel of experts from Improv Systems, STMicroelectronics, Philips, Cadence, Synopsys, and Mentor talked about "industrially proving" the SPIRIT consortium standards for design chain integration. SPIRIT is, of course, the 2-year old standards body supported by these companies, and others, which is attempting to develop a standardized wrapper for IP that will enable "machine integration" of said IP into the larger design.
The speakers on Thursday morning went into fairly exhaustive detail explaining how these particular players partner with each other - the pairing up being between an EDA provider and an IP provider or supplier - to produce IP wrappers within the SPIRIT specifications.
Philips had the most to say, which is perhaps not surprising. The bulk of the IP they were "wrapping" in their example was internally generated and being reused on other Philips projects. Even so, there is a great deal of anticipation about SPIRIT - and a great number of questions. Will the use of these standardized wrappers cause further lock-in between EDA vendors and their customers? Or is that perception erroneous? Will SPIRIT-designated wrappers, in fact, facilitate IP reuse and enable a larger market for third-party vendors?
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-- Peggy Aycinena, EDACafe.com Contributing Editor.