March 13, 2006
DATE 2006: Between Gemütlichkeit und Angst
Please note that contributed articles, blog entries, and comments posted on are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor

by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Nature itself came out to welcome the thousands who made their way to Munich last week to attend the 2006 conference on Design Automation & Test in Europe. The weekend prior to DATE, the skies let loose, the snows came down, trains, cars and trams were stopped, a plane skidded off the runway in Munich, and the city was covered in a snowfall so complete, the best thing to do was to take a long walk through the silent world to admire the outcome - presuming you had already arrived in Munich - and then retreat indoors for a hearty meal and a beer.

By Monday, the 6th, as Bavaria successfully dug out from under the heaviest snowfall in years, DATE got underway - offering attendees its usual warmth, hospitality, and excellent opportunities to learn both at a personal and a technical level. Unfortunately, those still enroute to Munich faced further delays or cancelled flights due to the weather, their troubles compounded by transportation strikes in various locales across Europe. Eventually most arrived (approximately 5000 people attended), and were glad they had persevered in order to attend DATE and participate in the conference, to see and be seen amidst the assembled design community there.

At a technical level, the conference was rich in content. General Chair Georges Gielen, Professor at the Katholieke Universiteit Leuven, told me the program committee received more paper submissions this year than ever before, just short of 900, and that DATE has come to be respected worldwide for the quality of its technical program.

Looking through the conference offerings - which ranged from design for manufacturing (DFM), networks on chip (NoCs), wireless sensor networks (a particular favorite of the Europeans), embedded systems, reconfigurable computing, and automotive electronics, to timing and noise analysis, on-chip power and leakage reduction, design verification, defect modeling, and nanotechnology, to mention a few - Georges Gielen and his committee, including Program Chair Donatella Sciuto, Professor at the Politecnico di Milano, could be justly proud of the depth and breadth of the DATE 2006 program.

It was not possible to attend everything - in fact, a number of attendees lamented that they could not be at more than one session at a time, and ended up having to choose between multiple, simultaneous offerings that all promised excellent content. This is not a problem unique to DATE, but a problem always associated with a conference of this size. Many highly informative sessions must run concurrently to present everything within 3 or 4 days. What follows are only a few of the highlights of my days at DATE 2006:

The keynote address delivered on Tuesday morning at DATE by Dr. Wally Rhines, Chairman and CEO at Mentor Graphics and Chair of the EDA Consortium (EDAC) was nothing short of a magnus opus. Rhines simply said it all - simply.

With the best slides I've ever seen, Rhines laid out the reality of the EDA landscape today - the types of companies, the economics of large companies versus small, the financial and technical impact of the innovation/acquisition cycle within EDA, how capital flows in and about the EDA ecosystem, how the tools are purchased and incorporated into the design flow, how the distribution of design starts between gate arrays, cell-based ICs, ASSPs, and FPGAs has varied over the last decade, and how the process technologies have evolved over the last 15 years.

Then, he illustrated the CAD tool purchase-and-use ecosystem structure within a company, and how the tensions are arrayed between software and hardware designers, system architects and chip designers, analog and digital designers, and designers and manufacturers. (see Saving the Best for Last below.) That complete, he graphically illustrated how EDA bridges all of these paradigms and eases the tensions therein. Now that last may have been more about the idealized EDA than the gritty reality, but the clarity of Rhines' presentation excused what might have been perceived as a simplification.

His keynote was simply great, and how do I know? Every single subsequent conversation that I heard at DATE referenced back to Rhines' talk on Tuesday morning. It was that simple, and it could not have been a better intro to everything that followed at DATE, particularly if you're interested in EDA.

** Tuesday morning, after the opening ceremonies and keynotes, Dataquest's Gary Smith moderated a panel that addressed "economic and strategic decision making for system design." Panelists included executives from Toshiba, Actel, Cisco, Tensilica, MathWorks, and Cadence. The group had some pretty snappy slides, and worked together well to provide a nice overview of the situation in ESL.

Toshiba's Armin Derpmanns summarized what is perhaps the single biggest issue facing the semiconductor industry today: "How do I incorporate all of the manufacturing and yield issues back up into my design work?" That may sound like a question that belonged on a design for manufacturing panel, but it actually fit well on the ESL panel, as well.

Actel's Dennis Kish enumerated other issues that add to the challenges: time-to-market pressures which abbreviate product-development time, constantly evolving standards which are difficult to track and implement, market demands for additional, sophisticated end-product features, consumer-driven pricing pressures, and the complexities of global suppliers and markets.

Tensilica's Chris Rowen, not surprisingly, said that multi-processor chips can help address these problems, plus alleviate some of the on-chip power problems facing designers today.

Cisco's Massimo Prati said additional solutions of "incredible elegance" include the use of advanced substrates, SIPs, and system-level-centric design philosophies - the actual point of the panel.

MathWork's Jim Tung - Gary Smith called MathWorks one of the hottest companies at the conference - said system-level design offers a plethora of advantages: opportunities for innovation, lowered project risk, better designer productivity, reduced development costs, shorter time to market, better team communication, and increased IP reuse. Gray Smith, the ultimate system-level design evangelist, beamed.

Finally, Cadence's Ted Vucurevich posed the uber-question: "Is semiconductor design improved by ESL?" Ted concluded that the answer is yes, particularly if system-level design is interpreted as platform-based design, with a dollop of model-based design thrown in for good measure.

In addition: Lunch at DATE is an amazingly delicious affair - good food and a choice of red or white wines served up to hundreds of people efficiently and graciously. Unfortunately, Gary Smith and I couldn't locate our meal tickets on Tuesday, and had to scramble to get sustenance with the help of some nice people at the registration desk. Gary ended up with little time to eat in the few minutes that fell between the end of his late morning panel and the start of his early afternoon event. I think if Gary's going to be asked to do 4 panels on a single day, somebody needs to make sure his meal is delivered to him personally - he shouldn't have to go looking.

** On Tuesday afternoon late in the day, competing for audience with the Executive track panel on DFM that included Synopsys CEO Dr. Aart de Geus, and Happy Hour out on the Exhibition Hall floor itself, I moderated a panel in the Exhibition Theater. The topic of the hour was how to balance design trade-offs between project specifications for power, performance, and programmability - the concept of 3D Design. LSI Logic's Mike Casey, CriticalBlue's David Stewart, CoWare's Johannes Stahl, and Ignios' Mark Lippett were the panelists.

As the discussion between the panelists unfolded, additional 'P' words were added to the list, above and beyond Power, Performance and Programmability. They included Platforms, Parallelism, Processors, Partitioning (between the hardware and software portions of a design), Prototyping, Prima Donnas (that would be both analog and digital designers), Pragmatic (reaching realistic design solutions within rational development schedules), Persuasion (important across inter-disciplinary teams), Price (always a concern), and Pain Point (that moment when new tools and/or methodologies are embraced).

1 | 2 | 3 | 4 | 5  Next Page »

You can find the full EDACafe event calendar here.

To read more news, click here.

-- Peggy Aycinena, Contributing Editor.

Review Article
  • October 09, 2008
    Reviewed by 'ashish'

    The author has given an excellent description of DATE 2006.

      Was this review helpful to you?   (Report this review as inappropriate)

  • October 09, 2008
    Reviewed by 'Couldn't make it to DATE'
    Very useful for those of us who couldn't make it to DATE. And Peggy always has a way of getting to the right people and to the essence of anything she's writing about. More detail than article coverage in some of the magazines, and the actual dialog was good to see. Thanks.
    And more from Peggy, please.

      Was this review helpful to you?   (Report this review as inappropriate)

  • October 09, 2008
    Reviewed by 'Joseph BOREL'
    Super article giving both the most outstanding messages and presentations and the ambient of the conference.
    I particularly appreciated the fact that start ups are considered in this paper because in such large conferences they are often simply ignored.
    I would really suggest that some very selected breakthroughs brought by the start ups be highlighted when significant added performance is demonstrated.
    I would have lowed to show to Peggy "a fantastic achievement" of EdXact (a new start up demonstrating during the conference, in front of Fenix booth of Hans) that simply adding a "filter" beyond the existing EDA companies extractions tools they were able to reduce the data of a factor of 10 as an average, without changing the simulation accuracy.
    A 10X gain in the volume of data is a 10X gain in simulation and verification that terribly decrease the cost of your verification/simulation tasks in the flow that accounts for nearly 30% of he overall cost of a design...transparently to your flow !!!!
    I can supply detailed information if needed.

      Was this review helpful to you?   (Report this review as inappropriate)

For more discussions, follow this link …
CST Webinar Series


Featured Video
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Acquiring Mentor: Four Good Ideas, One Great
More Editorial  
SENIOR ASIC Design Engineer for TiBit Communications at Petaluma, CA
Manager, Field Applications Engineering for Real Intent at Sunnyvale, CA
Upcoming Events
DeviceWerx - 2016 at Green Valley Ranch Casino & Resort Las Vegas NV - Nov 3 - 4, 2016
2016 International Conference On Computer Aided Design at Doubletree Hotel Austin TX - Nov 7 - 10, 2016
ICCAD 2016, Nov 7-10, 2016 at Doubletree Hotel in Austin, TX at Doubletree Hotel Austin TX - Nov 7 - 10, 2016
Electric&Hybrid Aerospace Technology Symposium 2016 at Conference Centre East. Koelnmesse (East Entrance) Messeplatz 1 Cologne Germany - Nov 9 - 10, 2016
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: UltraPLL

Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy