March 06, 2006
Yield Analysis Automation - LogicVision
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Jack Horgan - Contributing Editor


by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


Intel, Samsung, TI and Other Leading Semiconductor Vendors to Participate in China's Biggest IC Event More than 200 semiconductor companies will showcase their latest technologies at Global Sources' 11th International Integrated Circuit-China Conference & Exhibition (IIC-China) in March. IIC-China is expected to attract over 24,000 technology specialists. IIC-China will be staged in China's key electronics manufacturing hubs-in Shanghai on March 6 - 7; Shenzhen on March 10 - 11; and Beijing on March 13 - 14. It is held in conjunction with Embedded Systems Conference-China.


Sequence Revs Columbus-AMS for Faster, Better Wireless/High-Frequency Designs Sequence Design introduced the next generation of Columbus-AMS which is both a foundation for its RTL-to-silicon power-aware design tools, and its RLC parasitic extraction tool for high-performance, analog/mixed-signal design. New features include high-performance reduction controls and mixed-mode modeling capabilities to save time and simplify wireless and high-frequency design tasks


Poseidon Design Systems Appoints Brian Bailey as Chief Technologist Brian Bailey has served on the Poseidon Technical Advisory Board for the past year providing guidance and technically contributing to the direction of the company. He is the Chairman of the Accellera Interfaces committee. He has written two books and published many papers on the subjects of design and verification. Prior to this appointment Mr. Bailey was an independent industry and management consultant. He had previously been Chief Technologist for functional verification at Mentor Graphics.


Synopsys Introduces Pilot Design Environment Pilot Design Environment is a complete RTL-to-GDSII design system developed by Synopsys Professional Services and based on Synopsys' Galaxy and Discovery platforms. The environment is tapeout-proven at process nodes from 0.25 micron to 65 nanometers. It features implementation and functional verification flows, supporting the Discovery Verification Platform's VCS Native Testbench and Reference Verification Methodology (RVM), as well as the complete Galaxy Design Platform, including leading tools such as IC Compiler. Deployment service fees vary depending
on the amount of customization and associated project needs, and include the environment deliverables. An annual support contract is required.




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-- Jack Horgan, EDACafe.com Contributing Editor.


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