January 30, 2006
Zenasis Technologies – Hybrid Optimization
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Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
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First, it has worked out quite well. I've known Jay Roy since ViewLogic where we worked together for a couple of years. So I knew Jay very well. When you come to a company that has been going for 5 years and has developed such a large portfolio of technology, the real challenge that I saw was how do we take this shotgun approach and turn it into a rifle approach with respect to solving a well known problem in the semiconductor industry. That's what we have been focused on for the last six months; taking this portfolio of technology, finding out the jewels inside that portfolio and really honing them in on very specific problems in the semiconductor design space. The specific problem is
reducing the time it takes to do timing closure, quite frankly reducing not only the time but getting the design teams to become more efficient and effective in doing timing closure. The way we do that is by simply automating that process for them. A lot of timing closure today, as you know, is still done by hand because there aren't enough tools out there for engineers and design teams to do timing closure in an effective and efficient manner. That's what we have been focused on.

There are three generic approaches to design, FPGA, standard cell and custom ASIC. Is the standard cell approach just right or does it compromise too much on both ends to be a viable alternative to the others?

I think one of the reasons Zenasis exists and has been focused on this space is that the standard cell approach to ASICS is a compromise. If you have to push the limits of performance on your design and you are using the standard cell approach, then you will be compromising certain aspects of performance in terms of speed, power and area because of the very nature of the process. The initial thrust in terms of our position in the marketplace was to provide some of the benefits of custom design while at the same time using a standard cell approach. Most specifically the technology that we developed did design specific or tactical cell creation. That's where we see ourselves playing a
role. Most designs today are done using the standard cell approach. I think most of the design starts over the last several years have been standard cell that included embedded cores from the likes of ARM and MIPS. The challenge of course is because it is a compromise there is a risk in using the standard cell approach. You find design teams struggling to make the design run at spec. That causes delays to market and increase in cost. Any tool that can help the standard cell design team improve the time it takes to get to the performance spec is a valuable tool.

The Zenasis approach is called hybrid optimization

Hybrid optimization is one of the underlying patented technologies that the company has developed. There are other companies out there that attempt to help in that area but take a different approach. The hybrid optimization technology that is part of our optimization platform is one of the root technologies that enables us to solve that problem. More specifically, what hybrid optimization technology does is it analyzes the design at multiple levels of abstraction, namely the gate level, the physical level and the transistor level which is unique and it does this concurrently.

From browsing your website I sense that it tries to figure out areas that would benefit the most from tactical cell creation and then automates that.

It does several things. The key to this whole thing is to remember what design teams are up against. They have these very large, millions of gates, designs that have literally thousands of critical paths. To analyze that through manual methods is a daunting task, in fact next to impossible because of the nature of the approach they take. The first thing Zenasis does is to analyze the design. It does it at all of these three levels using hybrid optimization approach. The key to it is first identifying the path and then identifying the cells in those paths and then the type of cell that might break the bottleneck in that critical path to improve the timing. It does those three things simultaneously and automatically. The other interesting thing about the technology is that you will never get a worse result than you currently have. In other words it always improving the timing of the design or always improving the leakage power of the design. You never take a step back. With manual methods, as you now, because of the nature of the way you have to do it, it is possible that you go through this manual method, fix this particular path and then the timing of that path might improve but the overall timing of that particular block might not improve, In fact you might take a step back. With our approach of looking at all three levels (gate, transistor and physical) and
doing it on the fly, we never take a step back which is a great advantage using this type of tool.

Is "tactical cell creation on the fly" pulling existing cells from different libraries with different characteristics or is really creating something new?

There are two things that we do today. One is we can use hybrid optimization to identify the critical path and cells while taking into context the library. Think of it this way, you read in the design and the available library in and the tools tries to find in the first instance the best possible fit for a cell inside the existing libraries or a derivative of that cell inside that library to instantiate to make the timing better. That's level one. Level two is the tool will do the same thing, look at the library and then create an entirely new cell if necessary to improve the timing. So there are basically two modes. One mode where it looks at the design in the context of the
available cells in the design library and uses a more effective, a more efficient cell to instantiate to improve the timing And the other mode which tends to get much better performance in the end is to create an entirely new cell from an existing cell.

Are there certain markets or end user applications that would benefit most from your products?

I have been out and met with probably 50 prospects and a dozen or so customers. The design application where we see the best fit for the technology is where the design teams are struggling with high performance design, pushing the limits of the standard cell approach while using an embedded core from ARM or MIPS. The reason is they don't have complete control over the implementation of these cores. They have certain levels of control over the implementation but they bring in these cores from an outside source and they bring in other outside IP and then try to integrate that in. The challenge becomes how you make something perform at spec when you don't control all of the architectural
decisions that went into it. From that perspective we see people who are using embedded cores on high speed design. They have the greatest need for this application. ARM is a great example. Someone using an ARM would probably have a use for Zenasis products.

Do you have any relationship or partnership with ARM?

We are in discussion with several core providers including ARM and MIPS. We see that as a great opportunity for both Zenasis and these core providers to improve the timing closure process for our mutual customers. We see that as a very valuable relationship to create and then maintain.

Editor: Zenasis is a member in the ARM® Connected Community

You mentioned that Zenasis had been successful early in landing some key customers. Who are some of your customers?

I can't name a few for the obvious reason that they don't allow you to. I can say that among our customers there are some of the larger if not the largest DSP vendor on earth as well as some of the largest foundry companies. As an example TSMC is an investor. They will ultimately be a fairly large user of the technology. Companies like Renesas Technology and Samsung. At this point the company has been focused on a small set of core customers, particularly in the IDM space because of the need of having to do cell creation. But as we move forward, we have refined the technology to be applicable to a much wider audience
of customers and markets including fabless companies.

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-- Jack Horgan, EDACafe.com Contributing Editor.


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