October 24, 2005
TCAD - Technology CAD
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Jack Horgan - Contributing Editor


by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!




The top five articles over the last two weeks as determined by the number of readers were:


Syntest Receives "Multiple-capture DFT system for scan-based integrated circuits" Patent for At-Speed Scan/BIST InventionSynTest Technologies, Inc., was granted 33 claims under a US patent for its invention of at-speed testing of asynchronous multi-clock, multi-frequency designs, using ATPG or Logic BIST DFT schemes. The major benefit of this patented DFT scheme is the reduction in the number of ATPG patterns compared to the traditional one-hot DFT scheme for multi-clock, multi-frequency designs. The resultant compaction of 3x-10x translates directly into test cost savings.


Mentor Graphics Announces Third Quarter Results; Reaffirms 2005 and 2006 Guidance Mentor announced record revenue for a third quarter of $164.8 million. Earnings were break-even on a GAAP basis. For 2005, Mentor expects revenue of approximately $700 million and $755 million for 2006.


Asynchronous Circuits Transient Faults Sensitivity Evaluation - Technical Paper 151 The paper presents a transient faults sensitivity evaluation for Quasi Delay Insensitive (QDI) asynchronous circuits. The objective of this work is to evaluate the circuits robustness against natural faults (single fault model) and intentional fault injection (multiple faults model).


Kawasaki Microelectronics Adopts Apache's SoC Power Closure Design Flow 140 Kawasaki Microelectronics, Inc. will use Apache's RedHawk full-chip dynamic power solution in the design flow for ASIC designs at 130nm and below. Kawasaki selected RedHawk for its silicon-proven dynamic analysis of the power/ground network behavior and its ability to identify the impact of noise on timing and yield.


Synopsys Accused of Antitrust Violations in Magma Court Filing; Questions Validity of Synopsys Patents, Raises Question of Fraud 141 Magma claims that Synopsys' recent claims of patent infringement against Magma not only rely on patents that are invalid but also constitute a violation of United States antitrust law. Magama is disputing Synopsys' claims on the basis that the applications Synopsys made to the U.S. Patent and Trademark Office knowingly concealed relevant prior art that described the inventions claimed in the applications.




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-- Jack Horgan, EDACafe.com Contributing Editor.


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