October 24, 2005
TCAD - Technology CAD
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

What are some of the challenges that TCAD customers face today and how can TCAD mitigate these challenges?

Among the major challenges is the fact that the cost of production is rising, that technology complexity is increasing, that product lifecycles are decreasing and that process windows are shrinking.

It costs over $3B for a fab. When you run a 300 mm wafer through a production line it costs $20K. Anytime you can reduce the number of wafers you need to run in order to develop a process to meet the performance, you have a lot of savings by using the simulations rather than the actual wafers. Product development costs are going to be 3 times higher when you go from 90 nm to 65 nm and who knows how much more it will cost for 45 nm. If you look at the International Technology Roadmap for Semiconductors (ITRS) in 2004 there is a table that addresses the simulation and modeling aspects of technology development. According to this table you can save technology development costs up to 40% by 2006 when you use Technology CAD. A lot of our customers are taking advantage of TCAD in order to save the technology development costs. If you look at just a simple device the technology complexity is mind boggling, all the things you have to consider when you are looking at a new device or when someone passes you a performance spec for you to generate a chip. If you look at it, there are considerations of gate insulator, what kind of materials you should be using (high k or combined with silicon dioxide), what gate materials (poly or metal), how you can change the mobility in the channel for example by putting stress in the channel, how the doping can be activated, the cycle,
stress coming from trench isolation, what kind of materials you should be using for substrate (silicon, silicon germanium or SOI) and so forth. It is not easy to come up with all these things when you start to develop a new technology or a new process. Simulation allows you to look at different combinations, different design alternatives and putting them together and seeing what works and what doesn't work.

It's not a mystery that product lifecycles are decreasing. In the mid nineties when you were six months late, you might lose 31% of potential earnings. Today if you are 3 months late, you may lose the entire market in some cases. It is not easy when you are looking at a developing new technology to satisfy the performance spec for 65 nm or 45 nm while facing the time to market constraints as well. On top of that you have to look at new technology or new process steps. You have to look at new materials that are being introduced. Since analog and mixed signal requirements impact the yield pretty strongly, you need to look for innovative and advanced process control methodologies. When you have a shrinking process window, when you have to look at process variability and when you find that you have a problem with your yield, imagine going back and telling the designer to change his mask. It's another iterated cycle time. It takes time. It's pretty costly. So people are looking at a new way of doing advanced process control. Basically to look at the process sensitivity of your parametric yield so that you can analyze the sensitivity, control your process variability and improve your parametric yield. This is the new aspect of control that allows you to use TCAD for manufacturing, encapsulating the process parameters, correlating that with your parametric parameters
so that the manufacturing engineers can look at what would happen to your wafer and change some of the variables.

Terry shared with me an example of a fully depleted 20 nm FDSOI Mesa MOSFET. In this case one can use simulation is to explore how you can put the technology together, for example by introducing stress in the channel to increase the drive current. Through simulation one can look at many different types of formation of the gate trying to understand whether this technology will work and that it will meet the performance spec or not. In this particular case they were looking at the effect changing the germanium content in the source stream from 15% to 20%. They looked at different recess depths: 30 nm or 60 nm and then at the percent of underetching. They looked at where to introduce
stress in the channel in order to increase mobility. They used simulation to optimize the performance looking at the stress before the pre-spacer flow and after pre-spacer flow. In measurement, you have to do that on wafers. It is pretty costly and it takes a long time to run these experiments compared to simulation which you can easily do in a very short time.

He described another example application of controlling the process variability in a manufacturing line. In this particular case they were looking at an example a gating seeding that is out of spec. Once you take the measurements, you have to define what you want to do with the wafers. Do you want to continue to process them or stop the process? Remember that every wafer costs $20k to run through the production line. In the old days, if you had one wafer, the process engineer would say that's fine, stop this wafer and don't process it any more. But if you have a lot of wafers, let's say five different batches of wafers that are out of spec, what do you do? Now you have a way to look
ahead. If I change some of the process parameters like halo implant, if I change it to the high end of the spec will I be able to get the parametric parameters like on-current to be within spec? This is like a feed forward analysis. Instead of running wafers through the fab, now you have an instantaneous feedback on what will happen with these wafers if you change some of the process parameters down the road like implant energy so that you can save these wafers or not. It gives you a way to do advanced process control. Actually finishing these wafers will increase the number of good parts instead of slow parts. You can improve the yield that way.

Who uses Synopsys' TCAD offerings?

Our tools are being used by 19 out of the top 20 semiconductor firms. The other company has a lot of internal development on their own (you can probably guess which company it is). They are using some of our tools but not completely yet.

We have the industry's most experienced R&D and application teams. They can give you comprehensive knowledge about TCAD as well as the physics and numerical computation so that you can get very good simulation as well as the knowledge from our experts. We have a complementary consulting engineering service. For some customers to get started when they don't have enough resources to do the simulations or calibrations, we offer the service to help customers do that. We have a very strong R&D program with industry. As I mention the calibration aspect, the model parameters with equipment vendors as well as academia to look at the new physical models. We are not talking just about submicron
technology. We are talking about being able to simulate power devices, optoelectronics and so on and so forth.

All of this is aimed at being able to reduce silicon runs, run time and technology development costs.

What is the packaging and pricing for Sentaurus?

It varies depending upon the package. Our lowest priced tool, a visualization package is priced at $5,000. Our highest priced tool is 3D process simulation and is priced at $125K. That's a pretty big range. Typically for full process and device simulation capability you are looking at maybe $100K.

Does the average customer buy one package, one package for every manufacturing engineer, …?

Typically when you look at technology development area which is where the core TCAD is being used, we are looking on the average at 5 to 10 packages, especially when you are doing a lot of simulation runs during the optimization phase.

Availability of Sentaurus? October 17 <

« Previous Page 1 | 2 | 3 | 4 | 5  Next Page »

You can find the full EDACafe event calendar here.

To read more news, click here.

-- Jack Horgan, EDACafe.com Contributing Editor.


Review Article Be the first to review this article
Downstream : Solutuions for Post processing PCB Designs


Featured Video
ASIC Test Engineer for Butterfly Network at Guilford, Connecticut
Upcoming Events
The NAMM Show 2019 at Anaheim Convention Center Anaheim CA - Jan 24 - 27, 2019
IPC APEX EXPO 2019 at San Diego Convention Center CA - Jan 26 - 31, 2019
Defence Geospatial Intelligence 2019 at Royal Lancaster London London United Kingdom - Jan 28 - 30, 2019
3D & SYSTEMS Summit 2019 at Dresden Germany - Jan 28 - 30, 2019
DownStream: Solutions for Post Processing PCB Designs
TrueCircuits: UltraPLL

Internet Business Systems © 2019 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise