October 17, 2005
The Case of the Missing Via: Sequence Design
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Any other topic that my readers might be interested?
which the various power issues are becoming intimately intertwined with all the other issues. That's where we play, which is really the confluence of power, timing and signal integrity. CoolCheck is a new capability in that regard. CoolTime voltage drop optimization really draws in our strength in power, timing and SI, rolls them all together to come up with something that other people just can't do.
The top five articles over the last two weeks as determined by the number of readers were:
Cadence Announces Best Overall Paper Presented at CDNLive! Silicon Valley Conference; Six Additional Papers Receive Special Mention for Excellence at Tech-Heavy User Conference The best overall conference presentation -- chosen by the Cadence Designer Network steering committee -- was "IBIS Generation and Validation Methodology Using Spectre MDL". More than 200 abstracts were submitted, and 83 were selected for presentation at the conference, which drew more than 550 attendees.
Matlab as a Development Environment for FPGA Design - Technical Paper The paper discusses an efficient design flow from Matlab to FPGA. Employing Matlab for algorithm research and as system level language allows efficient transition from algorithm development to implementation.
FLEXBUS: A High-Performance System-on-Chip Communication Architecture with a Dynamically Configurable Topology - Technical Paper The paper describes the FLEXBUS architecture in detail and present techniques for its run-time configuration based on the characteristics of the on-chip communication traffic.
Floorplan-Aware Automated Synthesis of Bus-based Communication Architectures - Technical Paper The apaper an automated approach for synthesizing cost-effective, bus-based communication architectures that satisfy the performance constraints in a design. The synthesis flow also incorporates a high-level floorplanning and wire delay estimation engine to evaluate the feasibility of the synthesized bus architecture and detect timing violations early in the design flow. Case studies of network communication SoC subsystems are presented.
EDA Industry Reports Flat Revenue in 2nd Quarter of 2005 EDA Consortium's Market Statistics Service announced that EDA industry revenue for Q2 of 2005 was $1,091 million, versus $1,094 million in Q2 2004. Total product revenues, without services, were $1,028 million in Q2 of 2005 vs. $1024 million in the same quarter of 2004.
Other EDA News
Accellera Co-Sponsors GSPx, Offers Session on How PSL and SystemVerilog Improve IP Delivery and Verification
Phil Moorby Selected to Receive EDA Industry's Kaufman Award; Inventor of the Verilog Hardware Description Language Recognized as One of the Catalysts Behind Evolution & Growth of Electronic Design Automation Industry
Cadence Announces Best Overall Paper Presented at CDNLive! Silicon Valley Conference; Six Additional Papers Receive Special Mention for Excellence at Tech-Heavy User Conference
Other IP & SoC News
Samsung Electronics Announces 2005 Third-Quarter Earnings; Record Number of Handset Sales in the Third Quarter
EZchip and TeraChip Offer New Interoperable Processing and Switching Solution; New Solution Well Suited for Delivery of IP Video Services
The Demand for Increased Functionality, Improved Signal Integrity and Interconnect Density is Driving the Requirement for Flexible and Flex-Rigid Substrates
AMD Opens New 300mm Fab 36 in Dresden, Germany, Continuing Its Track Record of Flawless Manufacturing Strategy Execution
picoChip Launches Most Complete Family of WiMAX Reference Designs, Including Industry First for 16e; New Designs are First to Cover Fixed WiMAX (802.16d), Mobile WiMAX (802.16e) and Korean WiBRO
Spansion Announces World's First Single-chip 1 Gigabit NOR Flash Memory; First Samples Based on 90-Nanometer MirrorBit(TM) Technology
Cypress's New High-Speed USB 2.0 Microcontroller Has World's Smallest Package And Lowest Power For Mobile Phones, PMPs, PDAs and Webcams
SMC Ships First in New Line of Ultra-Efficient Single Chip Gigabit Ethernet Switches Powered by Agere Systems Ethernet Chips
Adaptec Strengthens SATA Product Line With New SATA II 4-Port and 8-Port RAID Controllers for Cost-Effective, High-Performance Storage
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-- Jack Horgan, EDACafe.com Contributing Editor.
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