October 17, 2005
The Case of the Missing Via: Sequence Design
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Jack Horgan - Contributing Editor


by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


Any other topic that my readers might be interested?

Feature size. These power problems become exacerbated as we go forward with technology. There's a couple of reason for it. One is naturally the line width becomes smaller. Not only does it become narrower but it also tends to become thinner because there is vertical scaling going on. That means the resistance of these routes goes up. That's just going to make it harder for power grid designers. Secondly, leakage current is going through the roof literally. I mentioned briefly about the gate leakage at 90nm and 65 nm. That's just one of the components. There are several other leakage components growing dramatically. What we are seeing is that it is becoming very difficult to pull out one single perspective or one parameter and fix that one alone. For example, decoupling capacitors. You can use these gate oxides capacitor but they are going to leak like crazy. They will leak even more as you go to smaller line widths. You can avoid that by using metal-to-metal decoupling capacitors but they are not as effective and you need better automation in terms of placement and sizing. That affects potentially your initial placement and how well you can close timing. What we are seeing as the line widths decrease is the whole design process is becoming more complicated. There's no news there. We've all known that. What is eye opening for some people is the extent to
which the various power issues are becoming intimately intertwined with all the other issues. That's where we play, which is really the confluence of power, timing and signal integrity. CoolCheck is a new capability in that regard. CoolTime voltage drop optimization really draws in our strength in power, timing and SI, rolls them all together to come up with something that other people just can't do.


The top five articles over the last two weeks as determined by the number of readers were:


Cadence Announces Best Overall Paper Presented at CDNLive! Silicon Valley Conference; Six Additional Papers Receive Special Mention for Excellence at Tech-Heavy User Conference The best overall conference presentation -- chosen by the Cadence Designer Network steering committee -- was "IBIS Generation and Validation Methodology Using Spectre MDL". More than 200 abstracts were submitted, and 83 were selected for presentation at the conference, which drew more than 550 attendees.


Matlab as a Development Environment for FPGA Design - Technical Paper The paper discusses an efficient design flow from Matlab to FPGA. Employing Matlab for algorithm research and as system level language allows efficient transition from algorithm development to implementation.


FLEXBUS: A High-Performance System-on-Chip Communication Architecture with a Dynamically Configurable Topology - Technical Paper The paper describes the FLEXBUS architecture in detail and present techniques for its run-time configuration based on the characteristics of the on-chip communication traffic.




Floorplan-Aware Automated Synthesis of Bus-based Communication Architectures - Technical Paper The apaper an automated approach for synthesizing cost-effective, bus-based communication architectures that satisfy the performance constraints in a design. The synthesis flow also incorporates a high-level floorplanning and wire delay estimation engine to evaluate the feasibility of the synthesized bus architecture and detect timing violations early in the design flow. Case studies of network communication SoC subsystems are presented.


EDA Industry Reports Flat Revenue in 2nd Quarter of 2005 EDA Consortium's Market Statistics Service announced that EDA industry revenue for Q2 of 2005 was $1,091 million, versus $1,094 million in Q2 2004. Total product revenues, without services, were $1,028 million in Q2 of 2005 vs. $1024 million in the same quarter of 2004.




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-- Jack Horgan, EDACafe.com Contributing Editor.


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