October 17, 2005
The Case of the Missing Via: Sequence Design
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Jack Horgan - Contributing Editor


by Jack Horgan - Contributing Editor
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Introduction


On September 26 Sequence Design introduced CoolCheck for formal power-grid verification. They claim that CoolCheck is able to detect errors that elude both static and dynamic voltage-drop analysis. CoolCheck employs a vector independent approach to examine power grids early in the design cycle, verifying both electrical and physical connectivity.


I had an opportunity to discuss this with company CTO and VP of Advanced Development Jerry Frenkil. Jerry was one of the founders of Sente, Inc. Sequence was formed in June 2000 by the merger of Frequency Technology and Sente in January of 2001. While at Sente, Mr. Frenkil was the Vice President of Low Power Design, where he led the services and applications activities. Prior to co-founding Sente, Mr. Frenkil was an independent consultant focused on IC design


Would you give me an overview of CoolCheck.

We have a new technology, a new product that we're calling CoolCheck. Basically what this does is that it is a tool for connectivity of you power grid. It's a power grid analyzer. It is not operating in the power space, in the power domain. It's not going to give you voltage drop. It's going to give you connectivity results. What it is doing is it is verifying the connectivity of all the cells to the grid. It does this without any simulation vectors. So that's why we are calling this a formal approach. The whole idea here is to catch errors that vector dependent methods might fail to catch. In that regard it really complements existing techniques from us and other vendors in the
static analysis as well as the dynamic analysis domains.


In CoolCheck we trace the path of every cell to the power grid. We compute how well connected that cell is to the grid. Our output is that we will point out where the electrical connections are weak. Because we are doing this without any kind of vector based power analysis, we can do this earlier. We can point out issues and errors to the power grid designer much more quickly in the design process than we could with conventional static or dynamic analysis.


The sorts of errors we point out to the designer are things like missing vias (probably the mjost common error) or circuitous connections to the grid. This might be a case where in fact the cells are connected but the path is very long and the path is not the intended path to the grid. In an extreme case, a complete power disconnect. These issues can be detected by static IR drop and dynamic voltage drop analyses but they don't necessarily find them all. The reason is that these techniques are all vector driven one way or another. If your simulation vectors or your stimuli don't stimulate a particular portion of the chip or a particular instance and if that instance is poorly
connected, you will never see it. In our approach as opposed to relying on external stimulator, we have a patent pending technique where we check every cell in terms of how it is connected to the grid, that way we are assured we are not going to miss any.


A visual example:




Here we are showing symbolically a couple of rows of logic. On the upper most row there's a power bus on either side in purple. The light blue is the power bus running through the cells. On the upper row we can see that the power bus is tapped on both sides while in the lower row, only tapped on one side. So that the cells that are highlighted are both in fact connected to the grid. The one on the lower row is poorly connected. The path to the grid has to go all the way through the logic cells to the power strap on the other side. This occurs from time to time because a via is missing or occasionally one via as opposed to what is called a via farm, an array of vias. In that case the
electrical connects are made but not made very strongly. This is a good example of the sorts of things, the particular category of areas that CoolCheck capture.


We can show the frequency of the problem, the statistics in the form of a histogram. The vertical axis is the number of instances and the horizontal axis the resistance. We are looking at how many instances are connected to the grid by a particular value of resistance. In a typical case the vast majority are well connected, the resistance to the grid is below 50 ohms. As one would expect there aren't too many that have resistance beyond 50 ohms. However, we might see a few around 120 ohms. These are things that one does not wish to see in a well designed grid for a chip. Usually these do not occur through design strategies. These are usually escapes, some kind of problem: a missing
strap, a missing via, that sort of thing. The far area or tail of the distribution is the area that designers want to look at. First of all they want to find out if there are any and secondly if there are, where they are and go look at them.


Does the CoolCheck software produce such diagrams?

The software does not produce this chart directly. However, we produce tables of this data. We have all the data. We list it more in an ASCII type of report. Users can script it up and search for tings.


We do generate what we call a thermal map not meaning temperature but rather it is color coded to indicate those areas that are problems. Red areas are those that designers would want to look at and see if there are particular design problems with regard to how the cells are connected to the grid. This enables designers to actually pinpoint where potential issues may lie.


We took a particular chip and ran it through CoolTime which is our dynamic voltage drop analysis tool as well as through CoolCheck. We plotted the results of both. There were some differences in these plots. The plot from the voltage drop analysis looks pretty good. There are some warm areas but the center of the chip looks pretty fine. However, the CoolCheck results indicate that there are areas in the center of the chip that are not well connected. The reason they didn't show up in the dynamic analysis is that that area of the chip is not really stimulated in the particular analysis. This is an indication that while dynamic analysis is certainly an important thing to do, it does
not necessarily catch all the problems. What CoolCheck is intended to do her is take a certain set of the problems and look at them exhaustively. Basically those problems are the strength of the connections to the electrical grid.


What are the inputs and outputs of CoolCheck?

Fairly conventional inputs: major physical design data base, LDEF, GDSII, Verilog Netlist, Synopsys.lib. The output is these thermal maps I have been describing and the detailed ASCIII reports. The former highlights the current path. You can go in and poke around in the display and find out what's their main current path for a cell through the grid.


Where does CoolCheck fit in the design flow?

The idea is really to perform a formal grid verification before you move into static or dynamic voltage drop analysis. Today designers typically do either a static IR drop analysis or first a static IR drop and than a dynamic voltage drop analysis or some are just relying on dynamic voltage drop analysis. The way we see this working together is that CoolCheck would precede both static and dynamic analysis. Once it passes the CoolCheck run and the designer is comfortable with the results then the grid itself is well designed. The questions, if there are any, that arise in static or more probably dynamic voltage drop analysis pertain to dynamic effects and are more power related as opposed to grid related. For example, you could have a well designed grid but still get dynamic voltage drop errors because you have too much ground bounce, too many cells switching at once, too much inductance due to package pins. In that case there is not a whole lot you can do with the design of the grid itself to fix that. You probably are going to need to change the design or add decoupling capacitors in the right places. We are trying to break the problem of power design and verification into different pieces. CoolCheck is intended to verify that the grid is electrically and
resistively robust. We offer some other techniques in dynamic voltage drop analysis and optimization which is not part of this announcement. CoolCheck is really intended to be a verification of the connectivity and the strength of the connectivity.


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-- Jack Horgan, EDACafe.com Contributing Editor.


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