October 03, 2005
Catching Up with MIPS
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Jack Horgan - Contributing Editor


by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


EVE Introduces Next-Generation Hardware-Assisted Verification Platform Series The first product in this series, the ZeBu-UF2 is an ultra-fast emulator that enables simultaneous hardware and embedded software verification. The ZeBu-UF Series can handle design capacity that ranges from 750,000 to six million application specific integrate circuit (ASIC) logic gates. Its memory capacity extends from 1.25 gigabits to four gigabits, and it has maximum performance that goes from 30 to 200 megahertz (MHz).


Structured ASICs to Solve Cost and Design Issues in the IC Industry Frost & Sullivan report on Emerging Trends in Structured ASIC/FPGA Technologies Impacting the Electronics Markets


LSI Logic Adopts Synopsys' New Design Planning Capabilities for Industry-Leading ASICs LSI Logic has integrated significant new capabilities of the Synopsys' JupiterXT Galaxy Design Planning solution into its FlexStream ASIC design flow. The key new features include automated macro placement and power network synthesis


Springer Publishes ARM-Synopsys Verification Methodology Manual for SystemVerilog Co-authored by ARM and Synopsys, the book documents years of know-how and industry best practices for architecting advanced, efficient verification environments using industry-standard SystemVerilog assertions, testbenches and functional coverage.




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-- Jack Horgan, EDACafe.com Contributing Editor.


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