September 26, 2005
New Physical Verification System from Cadence
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Jack Horgan - Contributing Editor

by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

When do you expect to release this for general distribution?

December! This is a technology announcement. We are still in developmental partner mode now for the next couple of months. In December we will ramp it up for full sales channel distribution and volume production.

What is the anticipated pricing for this offering?

It starts at $50,000 for a single CPU and scales upwards.

What is the upgrade price for customers that already have some of your DFM and physical verification modules?

In virtually all cases for large major customers they have some kind of relationship with us in place so there will be case by case upgrade consideration given as they look through the technology and decide how it applies for them. I don't have a one size fits all answer for you because there are so many different variations of installations of our customers from the more legacy tools.

Would a new customer at the lowest level configuration for this new environment be paying more than for the existing tool set?

In general when you buy more, you pay less per unit. Conceptually, if you're looking for a guide post, if you're buying a bundled configuration that has a lot more functionality, it would be more cost effective than buying as individual line items. Again it is difficult for me to talk generally about this.

Do you anticipate that a large number of prospects will already have compute farms?

Oh, yeah! Just about everybody big has one. Just about everybody medium size or smaller either has started to build one or rents one when they need it from IBM, HP or SUN.

The other thing that is neat about this - I don't know how closely you've looked lately at the hardware that is available out there. It's rather remarkable what $1,500 will but you in a blade these days. You are looking at a single or dual Opteron with a surprising amount of memory on it and some disk. For $1,500 to $2,000 a slice you can just keep adding these things into a rack. That's the essence of why this architecture seems to be exploding with our customers so quickly right now.

The lithography modules seem to be more of a post processing of a completed design than a DRC tool.

In some important ways it's less interactive though errors are found. There are applications for this type of technology that I was telling you about that involve litho rule checking where you will take on an actual post litho simulated result or even post OPC treatment, in other words the shapes are distorted as they will be printed, and run a checker against it to make sure that all of the litho critical dimensions and litho measurement points are still within tolerances. That's one application space for this class of technology.

If one finds an error, how far back does one go?

It depends. When you are in the litho treatment end of the world, the last thing you want to do is go back and talk to the design team. In some cases it happens but what you want to do is adjust the treatment or some parametric value on the engine to accommodate for the specific error you found. But sometimes you have to actually go all the way back to the design team to make the change. That's one of the reasons that those loops in the design flow are so horrifically expensive these days.

Are there any competitors out there offering distributed processing for physical verification?

I'm not exactly sure what other competitors are doing. I think Synopsys not too long ago made an announcement along these lines. I think that Magma made one as well. But we don't see them at any customer sites.

Was this technology home grown or the result of an acquisition?

There was an acquisition that took place about a year ago, a little company called eTop (ED: eTop Design Automation, a Beijing startup in August 2004). That's where one of the core DRC checking engines came from that we included in this environment. Virtually all the distributed processing and massive parallelism, concurrent reporting of results (I failed to talked about this earlier. ED: It delivers error data during runtime, via OpenAccess, into a Virtuoso-based debug environment. Designers can start to debug designs almost immediately after commencement of a physical verification run.), optimizing complier, all of the secret sauce I was describing is all pretty much home grown code.

Besides Fujitsu are there any other alpha sites, beta sites or early adopters?

There is actually a fairly large number right now. But there is nobody else where I am in a position to give names. We are working on a lot of projects that haven't taped out yet.

Are there any planned third party offerings in connection with this?

Nothing at this particular point in time.

What about the existing portfolio of DFM products? Dracula, ..?

Dracula is the original legacy DRC tool from the ECAD acquisition I mentioned 15 years ago whenever Cadence was originally formed. That tells you how long these things live by the way. It's not used on cutting edge designs right now but it's still around. People doing legacy incremental revisions of old chips, old military stuff but not cutting edge designs. But it turns out that there is a surprising market for Dracula in mainland China right now because a lot of those guys are using what we wouldn't consider cutting edge technology.

Before this introduction Assura was Cadence's mainline DRC solution. It worked fine for us up through about 130 nm. Customers did pretty well with it. But as we hit 90 nm and certainly as we are going to 65 nm, we came to the realization that we needed a whole new architecture to get it to scale and perform the way we wanted it to for the customer designs we saw coming.

What about Fire & Ice, Voltage Storm, ..?

As I mentioned before there is a lot of stuff in the DFM bucket. It's pretty much the whole spread of tools needed to extract, model and aggregate the behavior traits of design data with respect to its electrical characteristics and manufacturability. Most of these modules I would not consider mainstream with the new physical verification system.

The top five articles over the last two weeks as determined by the number of readers were:

Mentor Graphics Appoints New Vice President Mentor appointed Arun Arora as vice president and corporate treasurer. Previously Mr. Arora had responsibility for a significant portion of US sales and business development at Verari Systems. Prior to that, he was a senior member of the Corporate Development and Western Area Sales Operations Groups at Sun Microsystems. He has also held positions with companies including Credit Suisse First Boston and Goldman Sachs.

Class Action Lawsuit Against Synopsys Dismissed The class action lawsuit, filed in August 2004 in US District Court for the Northern District of California, had alleged securities laws violations by Synopsys and certain of its officers. Judgment has now been entered in favor of Synopsys with each party bearing its own fees and costs.

New Product Announcement: EverCAD to Deliver the Next Generation All-in-One Mixed-Signal Verification Solution, DIAMOND, for Complex Mixed-Signal SoC designers. Slated for ability early next month DIAMOND is designed for circuit level verification of designs with over millions of gates, including mixed-signal SoCs, video and network processors, DSPs, Flash, SRAM, DRAM, CAM and other memory-like structures. Also, DIAMOND's inherent strength is in its ability to accurately simulate Delta-sigma, ADC/DAC, switched-capacitor filters, PLLs (phase-locked loops), charge
pumps, high-speed transceivers and large analog designs which require long simulation times when using SPICE tools.

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-- Jack Horgan, Contributing Editor.

Review Article
  • October 09, 2008
    Reviewed by 'prag_79'
    A good article ,giving incite into the latest strategy employed by Cadence in develpment of high performance physical verification tool that can dramatically speed up design closure as claimed.

      Was this review helpful to you?   (Report this review as inappropriate)

  • Uploading avatar May 23, 2009
    Reviewed by 'greatterrakomp'
    Hello, everyone! Nice forum, nice discussions!

    Can you, guys, tell me how i can upload an avatar so that it could be displayed with all my posts? i'm just newbe in using forums and can't find this feature here.

    P.S. i'm sorry, may be i'm posting to the wrong category, but i just want to use all features of the board.

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