April 01, 2002
EDA Week in Review
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Ann Steffora - Contributing Editor

by Ann Steffora - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

At the top of the news this week was the rollout of Magma Design Automation, Inc.'s Diamond SI, an impressive standalone verification product that provides sign-off quality, post-layout analysis for a wide variety of signal integrity (SI) issues including crosstalk noise, crosstalk delay, voltage drop, and electromigration on both power and signal nets. Magma said Diamond SI accounts for the interdependencies between different SI effects, and eliminates the time-consuming and error-prone file exchanges required in point tool verification flows by integrating production-proven timing, extraction and analysis technology. Patented filtering techniques and analysis algorithms are
included, aimed at allowing designers to identify and focus on correcting true SI errors, and a universal SPICE interface enables highly accurate transistor-level analysis. With this integrated and comprehensive approach to SI analysis and verification, Diamond SI accelerates the typical post-layout sign-off verification cycle, Magma said.
Gary Smith, chief analyst at Gartner Dataquest said the tool looked pretty good. "Now that [Magma has] established themselves in the IC Implementation market they've targeted their effort on getting the slack out of the tool. They are allowing the engineer to increase the performance of the designs they can get using the tool," Smith added.
Diamond SI is based on Magma's single unified data model architecture and timing, extraction and analysis engines. This architecture provides the engines with full access to complete design data, allowing them to concurrently analyze for interdependent signal integrity effects without relying on complex, error-prone and time-consuming file-based interfaces. The static timing analysis and parasitic extraction engines have been production-proven by customers using Magma's Blast Fusion and Blast Chip systems.
Mentor Graphics Corp. announced the purchase of 7,836,636 shares pursuant to its tender offer for the publicly held shares of common stock of IKOS Systems, Inc. and the commencement of a subsequent offering period for the remaining shares at a price of $11.00 per share. Bottom line: Mentor has satisfied the tender offer condition that more than 50 percent of the fully diluted common stock of IKOS be tendered. Fresno Corp., the wholly owned subsidiary through which the tender offer was made, has accepted for payment all validly tendered shares and will make payment to the depositary for the accepted shares promptly.
Sequence Design, Inc. teamed with Fujitsu Microelectronics America, Inc. (FMA) in a joint development program to speed design closure of a 10 million gate, 200 MHz networking ASIC for a leading customer.
"With tight time-to-market pressures for our customers, we need tools like Sequence's PhysicalStudio to take our designers out of the design-iteration loop and move them to tapeout," said Tetsu Tanizawa, Fujitsu's director of worldwide design. "Our joint development with Sequence helped us achieve our complex, high-performance design objectives in record time."
Fujitsu's 10 million gate, 180-nanometer ASIC for a leading networking company contains complex, high-speed modules in an array fashion, a design that introduced many routing-congestion and wire-delay challenges at the top level, Sequence said. To free up more channels for the top level routing, the modules are packed into a very tight footprint, resulting in a highly congested layout. With the existing tools, this design often results in numerous iterations on the path to design closure. By adding PhysicalStudio, Fujitsu achieved design closure under this remarkably congestive condition for the two most difficult modules (which cover 80 percent of the chip area), while delivering a 30
percent improvement in timing.
Celoxica Limited announced the availability of DK1.1, the next version of its Handel-C-to-hardware design suite. DK1.1 includes new features for system-level HW/SW co-design, co-simulation support for ARM and PowerPC embedded processors, improved synthesis, enhanced area and delay analysis, improved VHDL output, Verilog output, 100 times faster simulation, and support for Actel, Altera Excalibur and Xilinx Virtex II Pro devices.
The DK1.1 design suite supports the design, validation, iterative refinement and implementation of complex algorithms in hardware. It includes built-in design entry, simulation, and synthesis - all driven by Handel-C. Handel-C is based on ANSI-C extended with concepts for timing, concurrency, flexible-width variables and resource allocation to let software engineers and hardware designers quickly implement complex algorithms efficiently in hardware, the company said.
Novas Software, Inc. unveiled the second generation of its debug technology platform that introduces new behavior-based debug and knowledge management capabilities, and delivers major architecture advances to double system performance and capacity. Currently in use at 10 customer beta sites, these advancements are expected to drive the next evolution in design exploration and debug for 10 million+ gate IC designs and also expand the benefits of faster, better debugging to the functional test programs associated with complex SoCs.
According to Novas, recent statistics on SoC design costs published by the International Technology Roadmap for Semiconductors (ITRS) project that one million dollars is added to the design budget for every month a project schedule slips.
Synchronicity Inc. announced the SoC Developer Suite featuring a solution to manage SoC designs hierarchically - the way engineers think. The SoC Developer Suite features new core technology including the Hierarchical Configuration Manager (HCM), which allows designers to work with design data at the chip, block and cell levels to speed development of very large SoCs, the company said.
With the HCM, each block can represent any level of the design hierarchy, from leaf cell through DSP core to the whole IC. Activities such as versioning the history of blocks and the chips that use the blocks, releasing blocks that have met validation criteria, and packaging blocks for re-use can now be performed in an intuitive, repeatable manner with the HCM.
Cadence Design Systems, Inc. and Chartered Semiconductor Manufacturing are working together to help mixed-signal designers reduce cycle times on designs with new Chartered foundry process design kits (PDKs). The PDKs will integrate Chartered's manufacturing processes for multiple nodes -- from 0.35 micron extending to 0.10 micron -- with the Cadence front-to-back design and verification flow for analog, RF and mixed-signal ICs, the companies said. The result is a design-through-manufacture path that helps companies meet aggressive product schedules for advanced mixed-signal SoCs.
To introduce the PDKs to the market, Chartered and Cadence will co-host a worldwide seminar series, "Acceleration to Technology Access," May 7-16. Additional information and online registration is currently available at

The PDKs will enable Chartered and Cadence customers to immediately begin designing chips rather than first developing their own required process design kits, the companies said. The PDKs provide a symbol library and technology file for the design automation flow and DRC-correct parameterized cells to automate device generation. They are validated with the Cadence Spectre models in the Cadence RF/analog mixed-signal design solution, which includes AMS Designer, Composer, Analog Design Environment, Spectre/Spectre-RF, Virtuoso Layout Editor and XL, Custom Placer, Custom Router, and the Assura/Diva physical verification suites.
Qualis Design Corp. announced its new verification methodology course "Expert Verification Strategies using OpenVera" for users of the OpenVera hardware verification language and Synopsys' VERA testbench tool. The new three-day course teaches engineers how to create advanced verification models and environments that leverage the powerful aspects of VERA, including constrained-random simulation, temporal expressions and functional coverage.

The advanced course covers the crucial aspects of advanced verification methods, including developing a verification plan suited for directed random verification; developing a verification environment that leverages directed random methods; using functional coverage to measure verification progress and use as feedback to direct testcase development; modeling data objects from an object-oriented approach; methods of constraining random generation to simplify controllability; designing bus functional models that support a directed random approach; and self-checking strategies for protocol-centric applications like datacom.
A detailed description of the course content can be found on the Qualis website at

Avant! Corp. reported that Specular Networks, Inc., a provider of high-speed integrated circuits, has chosen Avant!'s Star-SimXT simulator, a full-chip simulator with True-Hspice accuracy for simulation and post-layout sign-off verification. Specular said it is using Star-SimXT in the design of high-performance building blocks for the next generation of Internet infrastructure.
Sonics, Inc. today announced a new multiyear agreement that provides Broadcom Corp.'s Home Networking Business Unit continued access to Sonics' SiliconBackplane MicroNetwork for SoC designs. Under the previous one-year agreement, Broadcom successfully completed five multi-million-gate SoCs using the MicroNetwork intellectual property core. Broadcom plans to continue the use of Sonics MicroNetworks in some of its complex SoCs to simplify the integration and reuse of IP cores and to optimize on-chip communication. Financial terms of the agreement are not being disclosed.

You can find the full EDACafe event calendar here.

To read more news, click here.

-- Ann Steffora, EDACafe.com Contributing Editor.

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