April 27, 2002
EDA Week in Review
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Ann Steffora - Contributing Editor

by Ann Steffora - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

News and Analysis~

Consolidation Rules the Day With Acquisitions by EDA Market Leaders

Two large acquisitions topped the news last week: Cadence Design Systems, Inc. said it would acquire Simplex Solutions, Inc. for $300 million and Mentor Graphics Corp. agreed to acquire Innoveda Inc. for $160 million.
In the case of Cadence, the company said it will acquire Simplex in a tax-free, stock-for-stock merger with an equity value of approximately $300 million, or $18 per share of Simplex common stock, the price at the time of announcement, with the acquisition expected to be completed in 3Q02.
Ray Bingham, president and CEO of Cadence said in prepared comments that the company's strategy, "is to bring the best technology to market for 0.13-micron-and-below design. We have been building the solutions for the next generation of IC design for more than a year now. We are executing through our own innovation, accelerated by the acquisition of leading-edge technology from CadMOS, Silicon Perspective Corp. and Plato Design Systems. The proposed acquisition of Simplex fuels our efforts to supply our customers with the world's best technology to ensure 1st Silicon Success. Simplex's world-class technology and management team will be making significant contributions to the combined
The Simplex technology provides market-leading technology for 3D parasitic extraction and full-chip power-grid planning, electromigration and signal integrity, along with a design services capability that specializes in high-performance, multi-million-gate digital designs to complement Cadence's strengths in leading-edge analog and mixed-signal design, the companies said. Simplex also brings the X Initiative closer to Cadence, with the aim of improving design performance, power, cost and yield through the X Architecture interconnect technology.
When the merger is complete, Simplex chairwoman and CEO Penny Herscher will become executive VP and chief marketing officer responsible for marketing, strategy, Tality and the Simplex SoC Design Foundry, reporting to Ray Bingham. Aki Fujimura, Simplex president and COO, will become corporate VP and GM of the Design for Manufacturability business unit, reporting to Lavi Lev, executive VP and GM of the IC business unit. Steve Teig, Simplex CTO, will become the Cadence chief scientist and will join the office of the CTO, reporting to Ray Bingham.
Cadence also completed its acquisition of Plato Design Systems, Inc., which provides NanoRoute, a next-generation, graph-based router, that Cadence believes will improve its SP&R (synthesis/place-and-route) technology with performance, timing and signal integrity enhancements for 0.13-micron and smaller designs. Initially, NanoRoute will be incorporated as an option into Cadence SoC Encounter, Cadence's hierarchical IC implementation technology.
Regarding the Mentor Graphics acquisition of Innoveda, the companies agreed it would "significantly broaden [Mentor's] position in both the PCB systems and wire harness design markets" by integrating the Innoveda technology.
Just prior to announcing its agreement with Mentor Graphics, Innoveda said it was divesting its system-level design (SLD) software unit to Divestiture Growth Capital (DivestCap). The SLD business unit was created when Viewlogic and Summit Design, Inc. announced their merger in 1999, so it is interesting that Summit Design will return to its origins, and has reportedly begun operating again, as such. Larry Gerhard, once again CEO, will manage the born-again Summit Design.
What do the recent acquisitions of Silicon Perspective, Plato Design Systems and Simplex Solutions by Cadence mean? While some assert that it shows Cadence's weakness in developing its own tools, it is actually a wise business strategy in a day and age where research and development is many times more effective when it occurs outside large companies. It is clearly the make vs. buy decision - and for a market leader like Cadence, it is a smart strategy that has been successful in the past. And let's not forget that Synopsys Inc. and Mentor Graphics Corp. have made significant acquisitions lately as well.
Bringing in new blood to an organization can stoke the fire to rev everyone up, particularly when a recession can be a serious damper on spirits. In addition, the executives that Cadence will receive from Simplex are a huge benefit as well, based on their wealth of knowledge and industry experience. I think this gives Cadence a big boost in technological firepower in the future.
Is the picture as rosy for Mentor's acquisitions? Some financial analysts are questioning the strategy behind Mentor's recent acquisitions, trying to understand how the technologies all fit together. Time will tell.
In other news, sseveral leading electronics and EDA companies pledged support for the formal property language recently selected by the Accellera Formal Verification Technical Committee. The Committee selected the Sugar formal property language from IBM, which is the industry's first standard for formal properties, chosen after months of careful deliberation and debate by members of the Technical Committee, representing a wide variety of electronics and EDA companies.
Companies behind the language include 0-In Design Automation; @HDL; Cadence Design Systems; Co-Design Automation; Galileo Technology; IBM; Infineon Technologies; Mellanox Technologies; Mentor Graphics Corp.; NoBug Consulting; Novas Software; Real Intent; Structured Design Verification; TNI-Valiosys; TransEDA PLC; Veritable; Verplex Systems; and Zoran Corp.
The creation of the language is a collaborative action within the electronics industry aimed at enabling a new generation of verification tools, libraries, and methodologies united around the single language. Widespread adoption of the Accellera language is believed to enable an increase in productivity for EDA vendors and customers alike, as vendors can focus their resources to develop tools for a single formal property language, and customers can focus on using a common standard for developing property libraries that can be reused with tools from multiple vendors.

Xilinx, Inc. and Emulation and Verification Engineering (EVE), a French EDA startup, teamed to offer a family of high-performance co-simulation platforms, called ZeBu, for designs that fit in the high-density Virtex-II X2CV6000(TM) FPGA.
Luc Burgun, president and CEO of EVE explained that platform FPGAs, such as the Virtex-II devices, "represent a major advancement in the evolution of programmable logic devices and we are pleased to offer a unique and flexible validation platform for these high-performance devices. We believe that customers incorporating our design validation technology based on Xilinx's Virtex-II devices will be able to speed up the verification cycle by three to four orders of magnitude compared with the existing technologies." Launched at DATE2002 in Paris, ZeBu received a significant endorsement from five major electronic giants who signed up for an evaluation.
Altera Corp. and TSMC announced their technology collaboration based on TSMC's Nexsys technology for system-on-chip (SoC) design. The collaboration focuses on development of programmable logic devices (PLDs) at the 90-nanometer (nm) process node. Altera said it will leverage the Nexsys technology for future-generation PLDs and expects to realize a performance increase up to 30 percent as well as significant cost savings resulting from the combination of smaller die size and larger 300-mm semiconductor wafers.
Altera also announced that its Quartus II version 2.0 design software supports Red Hat's Linux version 7.1 operating system. Available immediately, this release is the industry's first native Linux port, allowing programmable logic device (PLD) designers to take advantage of more efficient distributed computing platforms, the company said and with this capability, Altera customers can use low-cost Linux-based server farms to reduce development costs and improve productivity.
Xpedion Design Systems, Inc. hired Richard Lazansky as VP of product development. Lazansky brings more than 20 years of commercial software development and engineering experience to the job. He will be responsible for leading the engineering team developing Xpedion's GoldenGate family of wireless/RF simulation products. Prior to joining Xpedion, Lazansky held engineering management and R&D positions with EDA companies such as Escalade, Denali Software, Vantage Analysis Systems/Viewlogic, and Silvar-Lisco. He has also worked for Intel as a programmer and for Stanford University as a student teaching fellow in computer science. Lazansky holds a BA degree in economics and
information science and an MS degree in computer science and computer engineering, both from Stanford University.
Monterey Design Systems today announced that Dr. Thomas Daniel has joined the company as VP of business development. In this newly created executive-level position, Daniel will lead the effort to forge strategic alliances with Monterey's largest customers, leading library and IP providers, as well as with other EDA vendors. Daniel reports to Jacques Benkoski, the company's president and CEO. Daniel joins Monterey from LSI Logic where he held a number of executive management positions, most recently VP of ASIC technology where he was responsible for the development and deployment of ASIC design tools, libraries and design methodology. Prior to LSI Logic, Daniel held
engineering management positions with Allen Bradley and with the French National Center for Scientific Research . Daniel received his MSEE at Warsaw Technical University and his Ph.D. from the University of Paris XI.
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-- Ann Steffora, EDACafe.com Contributing Editor.

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