May 20, 2005
EDA Week in Review
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Jack Horgan - Contributing Editor


by Jack Horgan - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

No single company can solve the design challenges that face the
electronics industry over the next decade. As an industry, we need to
start building better bridges between these databases on the way to
delivering on the promise of an interoperable infrastructure for our
customers.
Recently, the OpenAccess Coalition received consistently positive
response to its dedication to creating an open API, delivering open
source code and providing community driven change. Achievement of this
goal means significant interoperability among IC design tools to
accelerate time-to-market for electronics companies.
This leads us to issue the challenge that every database follows
the same path of having an open API, free availability of source code
and community managed change.
We invite you to join this quest for interoperability among
databases that will reduce the cost of selecting and deploying best in
class design technologies required to meet future design challenges.
If we all open our databases, the industry will reduce unnecessary
costs to the customer and allow the EDA and electronics industries'
combined energies to focus on addressing the complexity of chip
designs. This will provide significant benefits for both the EDA and
electronics industries.
Sincerely,
Lavi Lev

Cadence Design Systems, Inc.

Member, OpenAccess Coalition

More information about OpenAccess is available at

Incentia Design Systems, Inc. launched its physical synthesis product DesignCraft Pro, which delivers solutions from RTL to detailed placement with DFT and low power options and is a natural extension of Incentia's static timing analyzer, TimeCraft, and logic synthesizer, DesignCraft tools. The company markets the products as a unified, tape-out proven timing engine to ensure timing consistency between implementation and timing sign-off. Based on its patented technologies, DesignCraft Pro effectively addresses the issues of timing closure, design capacity, and turnaround time, for multi-million-gate nanometer designs, Incentia said.
DesignCraft Pro handles designs of up to 5 million gates on 32-bit platform workstations, and runs 2X to 5X faster than alternative solutions while producing superior timing results with setup time, hold time, design rule fix and area recovery, all simultaneously optimized. A 64-bit version is available for larger designs.
Novas Software, Inc. unveiled Verdi, a new debug and design exploration system that automates the time-consuming process of revealing the behavior of digital ICs. This development is a result of Novas' ongoing efforts to shorten verification cycles and increase engineering productivity to help design teams meet schedules and reduce project costs.
Verdi transforms the debugging process for leading edge IC and SoC applications with new behavior-based techniques that reduce the time and effort required to comprehend how a design works or why it does not work as expected, the company explained. Verdi is based on Novas' technology platform that delivers new technologies and methodologies for advanced design exploration and debug, knowledge management for design sharing and reuse, and integrated system-level design and testbench debug.
Antrim Design Systems, Inc. said its next-generation open environment for mixed-signal design will be called Antrim Aptivia. Formerly called Antrim ACV, Antrim Aptivia is a specification-driven design environment that provides an automated method for the analysis, characterization, and verification of analog and mixed-signal designs. Antrim Aptivia also introduces a new set of features that improve usability including a productivity saving test console, a Results Analysis and Display (RAD) tool, and enhancements to the window management.
Antrim also launched its Burst Licensing technology, a patent-pending enabler of distributed computing for simulation intensive operations. By enabling concurrent execution of multiple simulations, Burst Licensing offers designers a significant productivity boost while lowering their overall design cost. For example, a full characterization of an analog design may require simulations at 10 different load values, 10 supply voltages, 10 temperatures, and 3 processes resulting in 3000 simulations. Running these simulations consecutively can take days, even if each simulation only runs for a couple of minutes. Using Antrim's Burst Licensing model, the same job can be distributed over
multiple processors with inexpensive Burst licensed simulators to perform the overall task in a few hours. Thus, a single user is able to execute a design characterization quickly without having to acquire multiple full-feature simulator licenses at two to three times the cost.
Axis Systems, Inc. announced Xtreme-II, which simultaneously simulates, accelerates, and emulates system-on-chip designs containing up to 100 million ASIC gates.
According to Axis, Xtreme-II ushers in a new order for verifying today's most complex electronic designs: Platform Verification, an integrated functional verification environment supporting all levels of abstraction concurrently throughout the entire design flow. With Platform Verification, designers can, for the first time, simultaneously simulate, accelerate, and emulate their SoCs.
By having access to a complete verification suite in a single, unified environment, designers can better meet the challenges of larger and more complex designs, shorter schedules, and shrinking resources.
The event-driven ReConfigurable Computing (RCC) engine enables advanced debugging capabilities. Dynamic event processing techniques, when combined with RCC, efficiently harness the power of the largest commercially available FPGAs, resulting in the highest capacity, highest density, and lowest cost per gate. Simultaneous verification, with one system for simulation, acceleration, and emulation, deliver the maximum designer productivity. Abstraction binding enables model reuse and avoids costly model translations.
Accelerated Technology, the Embedded Systems Division of Mentor Graphics began shipping the code|lab Embedded Developer Suite for the ARMfamily of processors. This code|lab release includes support for the industry's most popular ARM core providers including ARM, Atmel, Cirrus Logic, Intel, NetSilicon and Samsung.
Accelerated Technology (AT) said it has supported the ARM family of processors with their Nucleus real-time software for more than 10 years. This code|lab release expands AT's Real-Time Operating System (RTOS) offering to developers building high performance, low power applications.
AT's code|lab Developer Suite is a set of software and hardware components that work out-of-the-box in a configuration that is customized to meet the exact combination of requirements for individual product designers. code|lab gives developers a flexible and seamless software and hardware tool suite in which to build their embedded application from start to finish and get it to market quickly. It is the only product of its kind to provide both software and hardware components in one ready-to-use kit.
Support for code|lab for the ARM family includes code|lab EDE, an embedded development environment, and code|lab Debug, a multitasking debugger, which supports a large variety of targets and connection devices. In fact, this version of code|lab supports more connections across ARM platforms than other debuggers in the embedded industry.
With this new code|lab release for ARM cores, developers building networking applications (ATM, broadband access platforms, RAID, remote monitoring and web switches) and wireless multimedia devices (PDAs, smart cellular phones and hand held devices that feature digital audio decompression) will greatly benefit from AT's latest out-of-the-box solution, the company asserted.
Advantest Corp. announced it is partnering with Mentor Graphics Corp. to ensure that Advantest's failure-diagnostics solution for deep-submicron, high-speed SoC designs is fully compatible with Mentor's suite of FastScan automatic test pattern generation (ATPG) tools. Advantest's SoC failure-diagnostics tool, currently under development and to be formally unveiled in September 2002, will use data communication between the company's T6000 series ATE systems and Mentor's FastScan ATPG tool to deliver fast, accurate pinpoint detection of failures in complex devices such as SoCs.
Nassda Corp. and Virage Logic Corp. announced the integration of Nassda's HSIM timing, power and signal-integrity analysis software into Virage Logic's Embed-It! software, an embedded memory design platform. The solution aims to accurately provide the performance characteristics of memory IP needed by SoC designers, thereby increases their confidence in achieving first-time silicon success.
With embedded memory increasingly dominating chip area, designers developing chips for applications in high-end LAN/WAN, wireless, networking, and portable digital electronics must accurately model the performance and power of embedded memories used in the chip. Virage Logic's Embed-It! memory compilation and characterization software, together with Nassda's HSIM circuit simulator, produces embedded memory IP that more closely reflects actual silicon. This simulation and analysis helps designers to achieve their requirements for power and timing performance of the chip.
Verplex Systems Inc. named ICON Design Automation Pvt. Ltd. of Bangalore, India, its exclusive distributor there. Founded in 1997, ICON Design Automation employs a dedicated team for marketing and selling the Verplex product line throughout India. In addition to post sales support they will also offer a fully staffed training center to serve local customer educational needs.
Synplicity, Inc. introduced its new MultiPoint synthesis technology targeting multi-million gate SoC and programmable system-on-a-chip (PSoC) integrated circuits. By providing a high productivity design methodology that is scalable to tens of millions of gates, Synplicity said the new technology addresses design challenges that are emerging as ASICs and programmable logic devices (PLDs) become more complex. Synplicity intends to deploy the MultiPoint technology within each of its ASIC and PLD synthesis products, and today announced its Synplify ASIC software is the first product to support the MultiPoint synthesis flow.

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-- Jack Horgan, EDACafe.com Contributing Editor.




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