June 03, 2002
EDA Week in Review
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Tim Unger to be Named President and CEO of Virtual Silicon Technology
Although it won't be formally announced until June 10, EDAToolsCafe has learned that semiconductor intellectual property supplier Virtual Silicon Technology, Inc., will replace founder, CEO and president Taylor Scanlon with industry veteran Tim Unger as the company takes “the next step in its corporate evolution from private to public status,” Scanlon said in prepared comments.
Reportedly, Scanlon is leaving the company to pursue other interests and will remain with the company in a consulting capacity during a transition period.
Unger has more than 20 years of experience in senior and general management roles in various technology markets, with previous industry experience including entrepreneur-in-residence with U.S. Venture Partners since 1997, and serving as CEO for several USVP portfolio start-ups including Nightfire Software and Intrinsa. Prior to USVP, Tim was senior vice president and corporate officer at Cadence Design Systems, Inc.
Mentor Graphics Corp. and Taiwan Semiconductor Corp. (TSMC) announced that Calibre DRC (design rule check) rule files are now available for TSMC's Nexsys 90nm technologies. The Calibre offering was enhanced by TSMC and Mentor Graphics engineering teams to interpret the leading-edge Nexsys 90nm design rules, which aim to exploit the most advanced capabilities of Calibre, ensuring that designers using TSMC's reference flow can rapidly verify their Nexsys-based SOC designs.
Synopsys, Inc. introduced an RTL Performance Prototyping (RPP) flow utilizing Physical Compiler, targeted toward IP providers and IP integrators, in order to enable IP providers to quickly characterize their soft IP against a complete set of end technologies, configurations and floorplans, and also dramatically reduces the time and effort required to integrate this IP into complex SoC designs, the company said.
yet faster timing convergence and routability.
Synopsys also released Design Compiler 2002.05, the latest version of its RTL synthesis solution, delivering up to 2X faster run times, 15 percent higher circuit speed, and 14 percent smaller area.
Design Compiler and Physical Compiler take advantage of the scalable flow and quality-of-results improvements in DC 2002.05, the company reported. For example, designers can see more than 10-fold improvement in the size of the largest synthesizable designs, stemming from memory usage improvements in DC2002.05, including Interface Logic Models, 64-bit support and further-automated divide-and-conquer flow.
Improved capability in DC Ultra leverage best-in-class datapath generation techniques popularized by the specialized datapath engine in Synopsys' Module Compiler.
DC Ultra 2002.05 contains a new set of optimizations that combines the benefits of resource sharing with the implementation of high-performance arithmetic components, results in an average of 10 percent faster and 14 percent smaller datapath circuitry without requiring the user to issue any additional commands.
A fully automated extraction of finite state machine (FSM) logic and a targeted set of optimization techniques deliver an average of 14 percent faster and 16 percent smaller FSM circuitry.
To address the use of gated clocks to reduce the power consumption of their designs, DC 2002.05 allows for automated register retiming combined with the power savings of clock gating.
Also, a new DC Ultra command, 'compile_ultra', encapsulates both the new and existing DC Ultra optimization capabilities to deliver an average of 11 percent faster designs.
Thirdly from Synopsys: Texas Instruments (TI) has standardized on the Synopsys PrimeTime delay calculator in its Pyramid ASIC design flow. With the adoption of the PrimeTime delay calculator, TI deploys a consistent, unified methodology for delay calculation and static timing analysis across its digital design flow, the companies said.
Built into Synopsys' PrimeTime and PrimeTime SI, the PrimeTime delay calculator provides cell and interconnect delay information that is required to achieve signoff-quality STA and signal integrity analysis. This technology is the foundation for static crosstalk analysis in PrimeTime SI, for accurate pinpoint crosstalk-induced timing failures on multimillion-gate designs.
Summit Design, Inc. announced resumption of full business operations as an independent EDA company. Summit Design is the former SLD business unit of Innoveda.
Guy Moshe, a founder of the original Summit Design, returns as president and CEO to lead a senior management team with more than 60 years of combined EDA experience. The company has a world-class engineering and R&D organization and will maintain and expand its worldwide sales, marketing, and distribution channels.
Summit Design's RTL and ESL products include Visual Elite (VE), HDLScore, Visual IP, VE System Design, VE System Architect, Virtual-CPU, and Virtual Prototype. These products span the full range of design issues from system-level to RTL code. The Summit product set provides ann environment, based on industry-standard languages, that support multiple abstraction levels and design domains and tools offer a bridge between HDL and C-based designs to increase design verification productivity by an order of magnitude for hardware/software-based systems.
Get2Chip, Inc. named three distributors to its expanding marketing, sales and support network: Maojet Technology Corp. from Taiwan, Saros Technology, Ltd. of the United Kingdom and Transfer EDA Group in The Netherlands. Under terms of each agreement, Maojet will cover Taiwan, Saros will handle distribution duties for the U.K. and Ireland, while Transfer EDA Group will represent Get2Chip in Belgium, The Netherlands, Luxembourg and Dusseldorf, Germany.
Cadence Design Systems, Inc. enhanced its Verification Cockpit offering with new Assertion-Based Verification (ABV) technology supporting the Sugar 2.0 Accellera standard language. Cadence also announced SystemC open language support, for design and verification in its NC-Sim and open-source TestBuilder products.
Mentor Graphics Corp. announced that Texas Instruments (TI) is adding Mentor Graphics Calibre physical verification tool suite for TI's ASIC, logic, mixed-signal and analog semiconductor processes. TI plans to use the tool suite to support key customers and technologies beginning late 2002.
Mentor Graphics also announced that the company's Calibre division has reached an agreement with IMEC, the leading European independent research center in the field of microelectronics, nanotechnology, enabling design methods and technologies for information and communications technologies (ICT) systems, to cooperate on the development of subwavelength microlithography.
IMEC will use the Calibre resolution enhancement technology (RET) software in a collaborative effort to advance high-numerical aperture (NA) 193-nanometer, and 157-nanometer (nm) microlithography processes. The use of RET software is the only way to enable acceptable chip yield at today's advanced process nodes.
This agreement formalizes the close, informal collaboration between IMEC and Mentor Graphics that has existed since 1999. Under the terms of the three-year agreement, Mentor Graphics will become a formal member of IMEC's industrial affiliation programs (IIAPs) for the development of high-NA 193-nm and 157-nm lithography and will continue to provide software, training and consulting. This collaboration will also ensure that Mentor Graphics RET keeps up with the demands of sub-100-nm technology, the companies said.
One of the areas of research that Mentor Graphics and IMEC will explore is in the double-exposure dipole decomposition resolution enhancement technique, which uses less expensive binary masks and still achieves very enhanced resolutions, similar to alternating, strong phase shift masking. This makes it a leading candidate for sub-100-nm strong RET.
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-- Ann Steffora, EDACafe.com Contributing Editor.
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