July 22, 2002
EDA Week in Review
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Magma also announced new design-for-test (DFT) capabilities for the Blast Chip RTL-to-GDSII design system are currently in beta testing and will be available in the fourth quarter of 2002.
The company believes that the addition of DFT capabilities to Blast Chip makes it the only EDA provider able to offer designers a single RTL-to-GDSII chip implementation system that integrates DFT analysis and repair capabilities with logic synthesis, and that is based on a unified data model architecture.
The DFT option to Blast Chip enables the system to insert test structures during design implementation, Magma explained, which ensures that the entire design, including the test structures, is optimized throughout the implementation flow for timing, area and power.
Thirdly, Magma reported that Faraday Technology Corp. would license its RTL-to-GDSII flow, including signal integrity capability, for deep-submicron ASIC design. This agreement follows Faraday's in-depth evaluation of Magma technology over the last few months, including several pilot projects aimed at defining a more productive design flow for Faraday's 0.18-micron and more advanced technologies.
Faraday and Magma said they would work together to integrate Magma tools with Faraday's in-house EDA tools, and construct design kits that incorporate Faraday's advanced ASIC cell libraries targeting wafer foundry, memory compilers, processor cores and other analog/mixed-signal IP blocks.
Developed in conjunction with Oki Semiconductorand the Pittsburgh Digital Greenhouse, Neolinear announced the availability of NeoIP, a soft analog IP library that can be used for analog and mixed-signal (A/MS) designs. NeoIP is used with the company's next generation A/MS design flow and is included with NeoCircuit, for automatic analog circuit sizing, and NeoCell for automatic analog cell place and route.
NeoIP contains sized schematics and verified layouts of analog circuits including popular topologies for voltage controlled oscillators, phase frequency detectors, opamps, etc. These example circuits have been sized to commercial specifications utilizing a generic process design kit. NeoIP circuits can be used to build complex analog blocks such as phase-locked loops or data converters. All designs have been automatically sized with NeoCircuit and placed and routed with NeoCell.
LogicVision, Inc. expanded its global distribution with the selection of D'Gipro Design Automation & Marketing Pvt. Ltd., as the exclusive distributor for LogicVision products in India. Under the agreement D'Gipro will sell LogicVision's Embedded Test 4.0 product line and provide marketing and technical service throughout India.
Monterey Design Systems announced that Dr. Olivier Coudert, senior technologist for Monterey, was recently presented with a "SIGDA Technical Leadership Award" for his efforts on behalf of the SIGDA (Special Interest Group on Design Automation) Ph.D. Forum. Coudert co-founded the forum 5 years ago.
The Ph.D. Forum is now the largest Ph.D. and industry exchange forum in the EDA industry. It is held annually at the Design Automation Conference. This year's forum at the 39th DAC in New Orleans drew more than 500 attendees. The Ph.D. Forum is a session hosted by SIGDA for Ph.D. students to present and discuss their thesis work with people in the design automation community. It is an opportunity for the Ph.D. students to get feedback on their work and for the industry to preview academic work in progress.
Coudert has been with Monterey for 4 years and is responsible for Monterey technology used throughout the entire product line - timing analysis, logic optimization, placement, and clock tree synthesis.
chip, an image processor and two wireline networking chips. Financing proceeds will be used to expand the company's physical design center and advance the technology.
Avnet Design Services (ADS), the technical arm of Avnet Electronics Marketing, and Xilinx Inc. announced a new development kit for the RapidIO interconnect, which includes a PowerQUICC MPC857T processor from Motorola and a Xilinx Virtex-II Platform FPGA, aimed at giving designers the flexibility to quickly and easily develop systems based on RapidIO interconnect technology -- accelerating the development cycle by as much as several months.
RapidIO interconnect technology is a switched, high-speed, low-latency packet-based, point-to-point mezzanine bus for processors, memory and IO. RapidIO technology reduces pin counts, while staying full duplex, and uses LVDS signaling.
The RapidIO Development Kit contains two Xilinx Virtex-II development boards, two Motorola 857T processor boards, the Xilinx Rapid I/O Physical Layer Interface, complete design documentation, demonstration programs, and a board support package to simplify application development.
Tensilica, Inc. hired industry veteran Paula Jones as director of corporate communications. Applying more than 20 years of experience in marketing communications, public and investor relations for numerous semiconductor and EDA companies, Jones will spearhead Tensilica's worldwide communications programs. Jones replaces Kim Alfaro, who retires after working with the company since shortly after it was founded.
Prior to founding her own firm, Jones held director-level positions with a variety of companies including MMC Networks, Synopsys and Cirrus Logic.
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-- Ann Steffora, EDACafe.com Contributing Editor.
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