August 24, 2002
EDA Week In Review
Please note that contributed articles, blog entries, and comments posted on are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Ann Steffora - Contributing Editor

by Ann Steffora - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Rumor of Synopsys Courting Co-Design Confirmed

Synopsys, Inc. finally announced it has signed a definitive agreement to acquire all outstanding shares of Co-Design Automation, Inc., developer of Superlog, after EDAToolsCafé.com reported the story over a month ago. Read the original article here:
Synopsys said that the combination of Co-Design's technology with its VCS Verilog simulator would enable delivery of next-generation hardware description language solutions. The deal consists of cash, notes and assumed options with an aggregate value of approximately $36 million, the companies said.
Co-Design developed SUPERLOG, an advanced language technology that extends the standard Verilog HDL with powerful high-level programming techniques and advanced verification and behavioral modeling capabilities that allow users to easily evolve their existing design and verification methodologies. This merger puts that technology into the hands of a company that can take it to the next level—providing designers with a level of support and productization that may not have been possible had it stayed with Co-Design.
The technology was created by some of the world's leading Verilog language experts, who had the insight and drive to think into the future. Synopsys chairman and CEO Dr. Aart de Geus said in prepared remarks that “having technology pioneers such as Phil Moorby, Peter Flake and Simon Davidmann join our team of verification experts significantly accelerates our Smart Verification strategy. The combination of Synopsys' recent VCS 7.0 release, SUPERLOG technology and the Accellera SystemVerilog umbrella will drive the state-of-the-art of RTL design and verification forward in very short order and decisively impact design productivity.”
Also, Intel and ARM publicly endorsed the merger.
Mentor Graphics Corp. was busy this week with a variety of announcements including a significant release of its front-to-back IC design tools for analog/mixed-signal (AMS) SoC designs with added functionality to existing tools as well as new tools.
The Mentor Graphics AMS SoC flow now includes Design Architect-IC (including a new AMS SoC design cockpit), ADVance MS (single-kernel simulator for analog, digital, transistor-level and RF simulation), IC Station (physical layout and implementation), Calibre (the industry standard for physical verification) and Calibre xRC (a new full-chip, transistor-level parasitic extraction tool).
For detailed information on the new tools, see the company's website:

0-In Design Automation released a new version of its CheckerWare library and monitors that supports Sugar -- the Accellera assertion language standard. 0-In said its CheckerWare library represents a family of complex assertion IP for on-chip interfaces and common register transfer language (RTL) structures such as arbiters, FSMs, and FIFOs. The library monitors, captures and checks the complete set of cycle-by-cycle protocol rules for complex industry standard buses, memory interfaces, and communication protocols including PCI-X, HyperTransport, PCI-Express, DDR SDRAM, POS-PHY, Utopia, and SPI-4.
The added Sugar support is meant to enable third party tools that support Verilog and Sugar, to understand and operate with 0-In CheckerWare. For tools that do not support Sugar, an equivalent IEEE Verilog version of CheckerWare is available so customers can mix and match tools that do and do not support Sugar in their assertion-based verification flow. CheckerWare with Sugar Support also enables designers to use 0-In's pseudo-comment specification syntax to place these Sugar assertions inline within their Verilog code.
Tensilica, Inc. announced its Xtensa V processor, a next-generation microprocessor core architecture that runs at 350 MHz in the worst case, and has support for multiple, unique processors in SOC designs. The processor also did well on a recent industry-standard Embedded Microprocessor Benchmark Consortium benchmark, Tensilica said. Xtensa is a configurable and extensible processor with automatic software, modeling and EDA support. Changes made by the designer to extend the Xtensa processor hardware -- adding instructions, registers, processor state and custom execution units -- are immediately and automatically reflected in the entire software tool chain, meant to reduce
design complexity and time-to-market.
Tensilica also said its new XT2000X Xtensa Microprocessor Emulation Kit for the new Xtensa V architecture is now shipping. Based on the Xilinx Virtex II Platform FPGA, the XT2000X Emulation Kit lets designers evaluate various processor configuration options in a system environment, as well as begin software development and debug much earlier in the design cycle. With this emulation kit and the Tensilica Xtensa V processor generator, the company reported that a designer could specify, implement and debug a new processor configuration in a matter of a few hours. This is the first Xtensa emulation kit based on the Xilinx Virtex II Platform FPGA. Tensilica also offers the XT2000A
emulation kit based on the Altera 20K1500E FPGA.
Semiconductor IP provider Sonics, Inc. added IP providers CAST, Inc. and 3rd Eye Technology, LLC to its partner list for its web-based SOCworks SOC evaluation environment. CAST is making its I2C, UART, MAC10/100 and USB cores available on SOCworks and 3rd Eye Technology is providing its authentication and encryption cores. The cores can all be combined with numerous other IP cores into a designer's system or SOC platform context using the site's graphical interface. Designers can then perform simulation and detailed evaluation prior to licensing the cores. All the new cores comply with the Open Core Protocol standard from the OCP-IP organization, a key enabler for their
secure evaluation on the website. Sonics also added a new behavioral modeling capability called QModels to the SOCworks site. QModels allow designers to create behavioral representations of their own proprietary IP cores so that they can be combined with the site's commercial IP cores in the simulation and performance analyses conducted on SOCworks. The intent of QModels is to help SOC designers assess their overall design concepts without having to host their most sensitive IP on the SOCworks site.
Esterel Technologies announced that Jean Marc Talbot, chief operating officer of Esterel Technologies, S.A., and chief executive officer of Esterel Technologies, Inc., has relocated from Paris, France to head U.S. operations in Silicon Valley. In addition, the company announced that Linda Prowse Fosler has joined the company as vice president of marketing. A new, expanded U.S. headquarters facility in Silicon Valley will enable Esterel Technologies to focus their efforts on the U.S. market, offer greater support to U.S. customers, and enable closer partnerships with leading Silicon Valley EDA and semiconductor companies, the company said.
Talbot was previously with Simulog, a French software firm, where for 10 years he specialized in technical computing and simulation. Prior to Simulog, Talbot was head of the scientific computing department at Schneider Electric in Grenoble, France. He began his career as an R&D engineer at Thomson-CSF in Paris. Talbot holds a MBA in Management from Ecole Superieure Des Affaires de Grenoble and a PhD in applied mathematics from the University of Paris.
Prowse Fosler was previously vice president of marketing and product operations for IKOS Systems, Inc. (now part of Mentor Graphics) and general manager of the Verification Solutions and New Technologies Group for the Mentor Emulation Division. Before IKOS, Prowse Fosler held various positions at Cadence Design Systems, Tandem Corp. and Hewlett Packard.
Prolific Inc. reported that it has joined the Synopsys in-Sync and TAP-in programs to ensure interoperability of Prolific's ProLiquid software with Synopsys' PrimeTime and Library Compiler tools, as well as with the standard Liberty modeling format.
Ansoft appointed Brad Cole to product marketing manager for its signal integrity (SI) line of tools. In his new position, Cole will market Ansoft's SI solutions. Before joining Ansoft, Cole was the marketing manager at Agilent Technologies' Signal Integrity Operation. Prior to that, he was the president of ATN Microwave, where he was responsible for all operational aspects of the company. Cole also has experience in RFIC product management and engineering from M/A-Com and Raytheon. He received a BSEE degree from Carnegie Mellon University, an MSECE degree from the University of Massachusetts, and an MBA from Boston University.
Magma Design Automation, Inc. released the preliminary agenda for its first Fusion user group conference. The meeting will be September 19-20, 2002 at the Westin Hotel in Santa Clara, Calif. and will feature tutorials, presentations and chat sessions given by Magma users, Magma's research and development staff and industry experts. The conference provides a forum for users to gain expertise using Magma systems and to exchange ideas about, and solutions for, the challenges of deep submicron IC and SoC design. The conference will also feature an exposition where Magma partners will exhibit products and services that are complementary to Magma
offerings. Attendees will be able to talk directly with Magma partners about design, flow and integration solutions.
1 | 2  Next Page »

You can find the full EDACafe event calendar here.

To read more news, click here.

-- Ann Steffora, Contributing Editor.

Review Article Be the first to review this article

Downstream : Solutuions for Post processing PCB Designs

Featured Video
Senior Electrical Engineer for Allen & Shariff Corporation at Pittsburgh, Pennsylvania
Upcoming Events
DAC 2018 at Moscone Center West San Francisco CA - Jun 24 - 28, 2018
Symposium on Counterfeit Parts and Materials 2018 at College Park Marriott Hotel & Conference Center MD - Jun 26 - 28, 2018
Concar Expo 2018 at Convention Hall II Sonnenallee 225 Berlin Germany - Jun 27 - 28, 2018
Nanotech 2019 at Tokyo Big Sight East Halls 4-6 & Conference Tower Tokyo Japan - Jun 30 - 1, 2018
ClioSoft at DAC
TrueCircuits: UltraPLL

Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise