August 30, 2002
EDA Week In Review
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Ann Steffora - Contributing Editor

by Ann Steffora - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Topping the news this week was Synopsys, Inc.'s announcement that its wholly owned subsidiary, Ferrite Acquisition Corp., is extending the expiration date of its offer to purchase all of the outstanding shares of common stock (par value $0.001 per share) of inSilicon Corp., at a price of $4.05 per share until 12:00 midnight E.T., on Thursday, September 12, 2002. The offer had been previously scheduled to expire on Wednesday, September 4, 2002. As of 6:00 p.m. E.T. on Wednesday, September 4, 2002, an aggregate of 14,242,405 shares of inSilicon common stock had been tendered to Ferrite Acquisition Corp. in the offer (including all of the 10,450,010 shares held by inSilicon's
majority stockholder, Phoenix Technologies Ltd.), representing approximately 93 percent of the outstanding shares of inSilicon common stock. The expiration date of the offer is being extended because the initial 30-day waiting period applicable to the pre-merger notification filing made by the parties under the Fair Trade Law of Taiwan has not expired nor has the Taiwan Fair Trade Commission made a decision not to exercise jurisdiction over the transaction.
Monterey Design Systems reported that NetLogic Microsystems has purchased its entire product line for planning, prototyping, and physical implementation for their next generation of classification and forwarding processors and network search engines.
Dolphin Integration released a new design architecture for embedded RAM and ROM, which the company said extends power optimization. The new generation of design architectures for RAM (4G) and for ROM (5.5G) is aimed at fabless suppliers and integrated device makers that rely on silicon-foundries or on proprietary fabrication lines, for battery powered SoC or ICs so large that power dissipation becomes an issue.

Sequence Design and UMC have teamed to complete the first ever silicon correlation of an interconnect self-inductance parasitic modeler. With this technology, UMC customers producing technology at 150 nanometers and below can be assured that high-speed analog and digital designs will have fewer failures due to interconnect issues. The Columbus R, C and self-inductance interconnect modeler libraries for UMC processes are available for download now on UMC's website.
UMC and Sequence said they developed a methodology to ensure accuracy of Sequence's Columbus technology. Tests were performed on a total of 30 die at 150 nanometers with plans for similar tests at 130 and 90 nanometers, each containing 25 unique interconnect self inductance structures. The S-parameters were then measured and converted to inductance values and correlated with the extracted interconnect self-inductance parasitic values. In all cases, the extracted inductances were within 10 percent of silicon-measured values.
The project sprang from a concern both companies had about the effects of inductance on timing and signal integrity due to interconnect issues arising from new, advanced processes, according to Vic Kulkarni, Sequence's president and CEO.

Also from Sequence – The company has appointed Dr. Susheel Chandra to the newly created position of senior vice president of research & development and product marketing, and Marianne Aguiar as senior controller and director of finance. Both positions report directly to Vic Kulkarni, Sequence president and CEO.

Chandra joins the company after eight years with Mentor Graphics, most recently as head of its intellectual property division, Inventra. Prior to that he conceived and built Mentor's R&D operations in India. Since receiving his doctorate in electrical and computer engineering from the University of Illinois at Urbana-Champaign in 1988, Chandra has held a number of increasingly responsible engineering, marketing, and management positions with companies including Sony, Checklogic Systems, and Crosscheck Technology. Chandra holds three U.S. patents, and plays an active role in several industry conferences and organizations, including DAC and VSIA.
Marianne Aguiar is a professional CPA with a long track record in finance and accounting. Prior to joining Sequence, she served as senior controller for Acirro Inc. in San Jose, Calif., a storage management software firm. A 1988 graduate of the University of California, Berkeley, Aguiar began her career with six years at Coopers and Lybrand in San Francisco. She then went on to a series of executive positions in and out of high-tech, including a stint as CFO for a Silicon Valley publicly traded real estate company, Mission West Properties.

Magma Design Automation Inc. announced that HCL Technologies (HCLT), India's leading technology services provider, has licensed Magma's Blast Fusion physical design system. By adopting Magma's integrated solution, HCLT said it would be able to extend its physical design capabilities to provide its design services customers with time-to-market, cost and productivity advantages for deep-submicron SoCs.

Nassda Corporation announced that Agere Systems is using the company's HSIM hierarchical full-chip simulator and analysis tool for advanced timing analysis of clock trees and memory characterization in its ASIC solutions. Under a multi-license agreement, Agere said it acquired HSIM to replace existing circuit-simulation tools.

Synopsys, Inc. also announced that NEC Electron Devices (NEC), has successfully verified its latest SONET/SDH framer physical layer chip with Synopsys' VERA testbench automation tool. NEC said that the advanced features in VERA such as its easy-to-learn, intuitive OpenVera hardware verification language, allowed NEC engineers to verify their design quickly and meet demanding schedules with a high quality, reusable verification environment.

The NEC SONET/SDH framer incorporates four, 622 megabit per second, synchronous optical network/synchronous digital hierarchy channels on a single chip, making it ideal for high-end WAN applications. Verifying the chip was complex, which necessitated the creation of a random stimulus generator. This shortened the verification time and achieved the desired coverage.

Axis Systems, Inc. today announced that PMC-Sierra has selected Axis Systems' Xtreme verification system to accelerate the development of PMC-Sierra's next-generation MIPS-based processors. Xtreme integrates software simulation, accelerated simulation, and emulation in one system, and enables designers to simultaneously verify the hardware design and develop software for target hardware, resulting in reduced verification time.

Xtreme is being used to design and verify hardware and software for PMC-Sierra's RM9000x2 1 GHz multiprocessor, targeted at networking applications such as edge and core routers, remote access products and enterprise servers, high-end laser printers and consumer appliances.

Altera Corp. introduced a new Stratix DSP development kit in order to provide DSP engineers with a comprehensive platform for designing, prototyping, and debugging high-performance DSP systems, the kit includes a development board, Altera's DSP Builder, Quartus II design software, and several system reference designs. The Stratix DSP development kit features a development board with a Stratix EP1S25 device, two 12-bit 125-MHz A/D converters, two 14-bit 165-MHz D/A converters, and 32 Mbits of flash memory. The Stratix DSP board features digital I/O connectivity, with four 40-pin connectors for Analog Devices' A/D converter boards and a separate connector for Texas
Instruments' TMS320 cross-platform daughter card. The kit also includes a 12-month license for DSP Builder and the Quartus II design software, a 30-day evaluation of MATLAB and Simulink from The MathWorks, and several system reference designs.

SynTest Technologies announced a software product called VirtualScan that employs a proprietary, patent-pending compaction technology that allows existing ATE resources to apply ATPG patterns through each external scan chain to a user-selectable, larger number of shorter internal scan chains. Using a large number of short scan chains reduces test application time and ATE memory storage requirement, without compromising product quality and extends the utilization of existing ATE for larger chip sizes, the company said.

Synplicity, Inc. announced that Texas Instruments Inc. (TI) has added Synplicity's FPGA synthesis and RTL prototyping software into its design flow. The companies signed a long-term licensing agreement granting TI worldwide access to Synplicity's current FPGA synthesis and RTL prototyping products. Under terms of the agreement, Synplicity will provide licenses of its Amplify Physical Optimizer, Synplify and Synplify Pro FPGA synthesis software and its RTL prototyping software, Certify and Certify SC, to TI for the design and development of FPGAs and FPGA-based prototypes for application specific standard parts.

Open Core Protocol International Partnership (OCP-IP) announced that semiconductor intellectual property (SIP) provider CAST, Inc. is joining the organization. CAST said it would use the OCP to enhance its broad line of general-purpose IP cores with the complete socket interface standard for SOC design. The tools granted with membership will also facilitate CAST's work with its international network of IP developers.

OCP-IP also announced that Virtual Silicon Technology Inc., another SIP provider, is joining the organization. Virtual Silicon said it would use the OCP technology to speed design cycles on its standard cell libraries, I/Os, specialty I/Os and interfaces, memory compilers, and PLL compilers.

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-- Ann Steffora, Contributing Editor.

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