September 06, 2002
EDA Week In Review
Please note that contributed articles, blog entries, and comments posted on are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Ann Steffora - Contributing Editor

by Ann Steffora - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Former HPL CEO Charged with Felony for Wire Fraud
More bad news for HPL Technologies, Inc.: Federal authorities charged the former CEO of the company with wire fraud for allegedly fabricating customer orders that represented most of the software maker's sales in the past fiscal year. The U.S. Attorney's Office for the Northern District of California alleged in a criminal complaint that Yervant David Lepejian repeatedly created fake customer purchase orders then covered up the fraud by doctoring financial records and forging letters to auditors verifying the sales. In addition, the Securities and Exchange Commission announced the former chairman and chief executive settled civil fraud charges for allegedly creating
more than $28 million in nonexistent sales that resulted in the company overstating its revenue for fiscal 2002 by 328 percent.
Synopsys, Inc. completed its acquisition of Co-Design Automation, Inc. and plans to, “further advance the development of a complete design and verification flow for SystemVerilog, the next-generation Verilog language,” said Manoj Gandhi, senior VP and GM of Synopsys' verification technology group in a public statement.
Cadence Design Systems, Inc. and Synchronicity Inc. inked a multi-million-dollar, three-year agreement that renews and extends their 1999 OEM agreement for design management software and maintenance. Under this new agreement, Synchronicity will provide development support, enhancements and maintenance for VersionSync, a basic version control solution for small, single-site, LAN-based IC development teams using the Cadence CIC tools. VersionSync will be upgraded to support Linux and 64-bit variants of Solaris and HP/UX. Cadence said it would make VersionSync available to all CIC users and be responsible for first level support.
Monterey Design Systems is expanding its sales and technical support organization with new offices in Italy, Boston, and Dallas, as well as additions to the West Coast sales staff. The addition of the new offices has created immediate openings for qualified applications engineers in Boston, Grenoble, Milan and Israel.
inSilicon Corporation is now shipping its USB On-The-Go (OTG) Controller Subsystem for consumer electronics and PC peripherals. The USB On-The-Go Specification is a supplement to the USB 2.0 Specification and adds Dual Role Device capability to USB devices. This allows a USB peripheral (device) to act as a mini-host, directly connecting to and driving a second USB device. For example, a USB device such as a digital camera implementing OTG can connect directly to an Xscale processor-based PDA and instantly transfer photos for viewing.

Esterel Technologies has partnered with France Telecom R&D and has integrated the France Telecom R&D Fast-C (SAXO-RT) compiler into its Esterel Studio product. The integrated Esterel Studio/SAXO-RT solution is meant to provide developers of embedded telecom applications with seamless development flow from specification to embedded C code.

iRoC Technologies announced SERTEST Shuttle, a turnkey test for soft errors in memory and logic ICs that measures the effects of alpha particles, thermal neutrons and atmospheric neutrons, replicated by a high-energy neutron beam. The result is a Soft Error Rate qualification for ICs to assure their highest reliability, availability and security in electronic systems. As more designs utilize 0.13µm and 0.09 µm processes, soft errors must be accounted for because they will occur randomly and are difficult to track, not easy to reproduce and almost impossible to model. Testing for both alpha particles and radiation induced neutrons enables designers to understand how soft
errors affect their circuits and then incorporate a solution before the product is released for manufacturing. Semiconductor manufacturers, system houses, fabless companies and IP providers are able to qualify their products with respect to an acceptable SER.

eInfochips and Verisity Ltd. said they are working with Intel Corporation to deliver a PCI Express e Verification Component (eVC). eInfochips, a member of Verisity's Verification Alliance partners program, will develop the eVC. To ensure that the eVC delivers complete protocol checking, Intel plans to provide PCI-Express enabling tools to eInfochips. Verisity said it would certify the eVC's compliance with the e Reuse Methodology to ensure that it will plug-and-play with all other eRM compliant eVCs. eVCs are reusable plug-and-play verification components for standard protocols and interfaces, based on Verisity's high-level verification language, e, and the Specman
Elite testbench automation tool.

Verisity and Be One Lab Inc. are shipping three new e Verification Components from Be One Lab. SONET/SDH, SPI4, and UTOPIA4 are Be One Lab's initial offerings of reusable, plug-and-play verification components for standard interfaces based on Verisity's high-level verification language, e. These eVCs, which were developed using Specman Elite, will be eRM compliant by Q402, meeting the standard requirements for full interoperability with all other eVCs developed using Verisity's e Reuse Methodology.

Verisity and Cold Spring Engineering announced the availability of a new e Verification Component from Cold Spring Engineering. The SPI 4.2 eVC is the newest addition to a growing list of configurable, reusable, plug-and-play verification components for standard interfaces based on Verisity's high-level verification language, e. This eVC, developed using Specman Elite allegedly reduces the time necessary to create the verification infrastructure and automated testbench environment.

Verisity and HCL Technologies announced the availability of an e Verification Component for the ARM7 ISA standard. eVCs are reusable plug-and-play verification components for standard interfaces based on Verisity's high-level verification language, e. HCL Technologies' new ARM eVC contains verification capabilities for the ARM v4T ISA, meant to cut verification environment development time.

Amphion Semiconductor, Inc. has developed ASIC- and FPGA-targeted versions of its hardware-accelerator cores for MPEG-4, MPEG-2, and JPEG2000 compression with AHB interfaces compatible with the AMBA specification for on-chip system bus connectivity. The provision of Advanced High-Performance Bus (AHB) interfaces is aimed at enhancing the applicability of Amphion's silicon-efficient core solutions to AMBA-based SoC designs, such as those leveraging RISC microprocessor cores from ARM and other processor IP providers.

Celoxica Ltd., Motorola and StrongBow Technologies are working together to create servers that embed applications, such as transaction processing for credit cards, directly in hardware. StrongBow's modular server technology is designed around Motorola Computer Group's MXP platform and the proposed PICMG 2.20 standard for a high-speed serial mesh interconnect. The platform carries boards with multiple Xilinx Virtextm-II Pro Platform FPGAs, for massively parallel hardware implementation of applications, which are programmed using Celoxica's DK1 design suite. Customers can quickly and confidently design, implement and manage business critical applications.

Synopsys, Inc. announced that the Avant! tool Hercules now provides design rule check (DRC) rule files for TSMC's Nexsys 90 nanometer process technology. Through a collaborative effort with Synopsys' physical verification specialists, TSMC design services engineers have developed Hercules rule files for DRC and layout versus schematic (LVS) checking. These rule files are meant to enable designers to verify their designs quickly and easily for TSMC's most advanced process technology, the companies reported.

LogicVision, Inc. announced VIA Technologies Inc. of Taipei, Taiwan has adopted LogicVision's Embedded Test technology for its next chip designs. LogicVision said it is pleased to add VIA Technologies to its list of new customers and look forward to working with VIA Technologies to enhance their device development with its Embedded Test technology.

Actel Corporation launched a website dedicated to the growing problem of design theft and lack of awareness in the industry. The Actel Security Resource Center ( provides customers, design engineers and managers with information on the fundamentals of security issues and secure FPGA solutions, including technology tutorials, market overviews, white papers, government links and extensive glossaries. Actel believes the website will enable the design community to increase its awareness of critical design principles, methodologies and common security threats, such as overbuilding, reverse engineering, cloning and denial of service.

Silicon Metrics Corporation announced an agreement with Tritech Systems Inc. for exclusive rights to represent Silicon Metrics for the marketing, sale and support of the entire SiliconSmart product line in Korea.

Cohesion Systems, Inc. announced one-year term subscription licensing for their Chip Designer and System Designer product lines. Cohesion Chip Designer provides a design and debug workflow for Custom IC, Analog and Mixed Signal in multi-user design environments, supporting industry standard simulation, synthesis and layout flows. System Designer is for the design of complex boards and multi-module systems, optimized to drive the Allegro design flow.

To read more news,
click here .

You can find the full EDACafe event calendar here.

To read more news, click here.

-- Ann Steffora, Contributing Editor.

Review Article Be the first to review this article

Featured Video
Senior Electrical Engineer for Allen & Shariff Corporation at Pittsburgh, Pennsylvania
Principle Electronic Design Engr for Cypress Semiconductor at San Jose, California
Director, Business Development for Kongsberg Geospatial at Ottawa, Canada
Director, Business Development for Kongsberg Geospatial at remote from home, Any State in the USA
Upcoming Events
IPC Technical Education - PCB Layout - Place and Route at Del Mar Fairgrounds 2260 Jimmy Durante Blvd. Del Mar CA - May 2, 2018
IPC Technical Education at Wisconsin Center 400 W Wisconsin Ave. Milwaukee WI - May 8, 2018
IPC High Reliability Forum at Embassy Suites: Baltimore-At BWI Airport 1300 Concourse Drive Linthicum MD - May 15 - 17, 2018
TrueCircuits: IoTPLL

Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise