October 14, 2002
Apache Unveils Next-Generation Power Integrity SOC Tool
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Ann Steffora - Contributing Editor

by Ann Steffora - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

The deadline for proposing papers for the Design & Verification Languages Conference and Exhibition (DVCon) is October 15, 2002. DVCon 2003 will be held February 24-26, 2003 at the DoubleTree Hotel in San Jose, California.

DVCon is the new name for the HDL/OVI conference, which will celebrate its 12th anniversary session in 2003. (It began as Open Verilog International and then merged with the VHDL International to become the International HDL Conference.) HDLCon's scope may have started with Verilog and VHDL, but the conference scope has evolved as new languages have emerged, to now include VERA, E & SystemC.

Proposals are invited for any of the following types of presentations:
  • Technical papers on using Hardware Description Languages (HDLs)
  • Technical papers on using Hardware Verification Languages (HVLs)
  • In-depth tutorials on design and verification techniques
  • Educational panels on trends in design and verification
  • Details on submitting a paper, tutorial or panel proposal, along with suggested topics, can be found on the Design & Verification Conference web page at
    The 11th IP based SOC Design Workshop will take place in Grenoble, France on October 30 and 31, 2002. Among 100 submissions the best technical contributions have been selected to bring together a high level working conference unique on hot topics such as “Impact of Submicron Technology,” “IP Management and Collaborative Design,” “Verification IP,” “IP Business Models,” and “Platform Based Design and Embedded System.”
    The program has outlined most of the foremost players actively involved in this field planning to deliver their latest products and major fact announcements at this event. Please refer to the Online Program:
    Keynote speakers include: John Chilton, senior vice president and general manager of Synopsys IP and Systems business unit, Michael Kaskowitz, General Manager and VP of the IP Business unit of Mentor Graphics, Thierry Pfirsch, Core Competence Manager for IP at Alcatel and Jim Tully, Chief Analyst from Gartner Dataquest.
    On October 31st the “Best IP/SOC” trophy sponsored by ST Microelectronics will be given involving a selection among eight candidate companies. In addition the “IP based SOC Design Workshop” has an exhibition attached include Accent, Artisan Components, Axis Systems, Cadence Design Foundry, CoWare, Denali Software, Design And Reuse, Dolphin Integration, Ericsson Technology Licensing, GeTeDes, Infineon Technologies, Jennic, OCP-IP, ProDesign, SuperH, Synchronicity, Synopsys, VCX and Verisity.

    To read more news,

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    You can find the full EDACafe event calendar here.

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    -- Ann Steffora, EDACafe.com Contributing Editor.


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