November 11, 2002
Ron Rohrer Chosen as 2002 Phil Kaufman Award Winner by EDA Consortium
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Ann Steffora - Contributing Editor

by Ann Steffora - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

The EDA Consortium chose electronic industry pioneer, entrepreneur, researcher and educator Ron Rohrer as the 2002 recipient of its Phil Kaufman Award. Rohrer is chairman of Neolinear and was selected for his contributions to the EDA industry. The Consortium will present the Award on Tuesday, November 12, at its annual award ceremony at the Fairmont Hotel in San Jose. The Phil Kaufman Award honors individuals who have made a substantial, sustainable contribution to the success and advancement of the EDA industry.

Rohrer is a world-renowned expert in the semiconductor and EDA industries, and has been a key advisor to Neolinear for the company's next generation custom IC design automation technologies, products and business since 1999.

“Ron is not only chairman of Neolinear, but an active participant in research and product creation. Currently, his experience, knowledge and creativity are being applied to automation techniques for high frequency design,” said Tom Beckley, president and CEO of Neolinear. “Neolinear is very fortunate to have Ron on our team, and the EDAC recognition is well deserved based on his contributions to our company and the EDA industry overall.”

Rohrer started his industrial career at Fairchild Semiconductor in the 1960s, and has since served as technical consultant and advisor to many leading EDA and electronics companies. Rohrer is an entrepreneur, who has been involved with a dozen successful start-up companies and an educator who has taught at leading universities. He has authored five textbooks and more than one hundred papers, and is a Fellow of the IEEE and a member of the US National Academy of Engineering. He was awarded the IEEE Education Medal in 1993, and the C&C Prize in Japan in 1996.

Product News

Synplicity, Inc. enhanced its Synplify Pro FPGA synthesis software to further address the critical challenges confronting designers of highly complex PLDs by adding its MultiPoint technology and timing analysis capabilities in order to improve performance and quality of results, the company said.

Synplicity said its MultiPoint technology enables a difference-based incremental synthesis approach, which eliminates the need for re-synthesis, which is common with time-stamp-based incremental flows, by only re-synthesizing design entities that will have a different gate-level netlist due to code or constraint changes. The MultiPoint flow also offers support for designers using the Xilinx ISE Incremental Design Flow and the Altera LogicLock feature within the Quartus II design software.

Synplify Pro 7.2 includes timing analysis capabilities integrated into its HDL Analyst software that enables designers to identify critical paths quickly and perform fast, interactive timing analysis without re-synthesizing their design. The new timing analysis feature allows users to incrementally specify from-to paths in their circuit for instant detailed analysis saving time and improving productivity.

Also, Synplify Pro offers a mode of operation that is compatible with the Verplex Conformal LEC (Logical Equivalency Checker) tool. Synplicity and Verplex have established an optimized programmable logic design flow, meant to provide designers with a highly integrated solution for verifying designs created by Synplicity's Synplify Pro software using Verplex's Conformal product.

Ansoft Corporation released SIMPLORER 6.0 simulation software designed for the digital prototyping of multi-technology systems used in the automotive, aerospace, and power-electronics industries.

SIMPLORER's capabilities, features, and quality of support meet the goals and fit well with the simulation vision and strategy of DaimlerChrysler and would help to streamline and accelerate the electrical design process for conventional and electric/hybrid-electric vehicles, the companies said.

SIMPLORER 6.0 is a software environment built on a co-simulation technology, which is meant to enable engineers to accurately model systems comprised of analog, digital, mixed-signal electronics, mechanics, hydraulics, controls, and other technologies without having to choose between proprietary modeling languages. SIMPLORER allows all of these technologies to operate simultaneously, delivering power and flexibility for simulating complex multi-technology systems.

UK-based design consultancy Cambridge Consultants LLC (CCL) released CCLasic, a silicon intellectual property (IP) library for SoC and ASIC applications focused specifically on mixed-signal building blocks including lean CMOS software-defined radio and processor cores. Optimized for low cost and low power, these circuits can deliver wireless connectivity to new applications in cost-critical market segments including industrial instrumentation, toys and consumer goods.

The company said its library is a family of interoperable components for mixed-signal control and communications applications, which have been field-proven on design projects, many involving multi-million production quantities, in order to address the single most important criteria in selecting IP following a component's fundamental performance – the availability of all functions required from one supplier.

Since many of the target applications for this technology are in organizations with limited experience of embedded system design, CCL is supporting the launch with development services including turnkey design of entire products if required.

CCLasic incorporates three main categories of silicon IP for ASIC and SoC applications: radio, processor, and data converter functions, which total over 20 building blocks. Each comes with documentation and support including test routines. Analog designs are provided as hard macros, for processes including 0.35 and 0.18 micron. The blocks are suitable for fabrication by commercial CMOS foundries, and can be ported on request to other geometries/processes. Digital circuits come in the form of synthesizable, process-portable, Verilog RTL.

Altera Corporation customers now have access to MorethanIP's portfolio of 10-Gigabit Ethernet IP cores. Optimized for Altera's recently announced Stratix GX device family, the cores give designers a solution for a range of 10-Gigabit Ethernet applications such as LAN PHY and WAN PHY. The Stratix GX device family was designed for easy implementation of the XAUI protocol to help designers meet the challenges posed by high-speed 10-Gbps applications now moving into wide deployment.

MorethanIP's 10-Gigabit Ethernet IP core library includes:

10-Gigabit Ethernet XAUI MAC (Media Access Controller)

10-Gigabit Ethernet MAC with FIFO (with Atlantic(TM) interface)

10-Gigabit Ethernet 10GBase-R PCS (Physical Coding Sub-Layer for LAN
PHY Applications)

10-Gigabit Ethernet 10GBase-W PCS (Physical Coding Sub-Layer for WAN PHY Applications)

Gigabit Ethernet MAC with 1000Base-X PCS
Amphion Semiconductor, Inc. extended its CS6700 series of high performance cores for low power MPEG-4 enabled applications with an advanced modular accelerator-based solution for real-time MPEG-4 video compression. The company believes MPEG-4 technology is set to make an enormous impact in digital video and streaming media applications as diverse as game consoles, digital camcorders, multimedia PDAs, 3G mobile phones, digital TV and cinema.

Designed for ultra low power operation and easy system-level integration into processor-based SoC and platform solutions, the Amphion CS6701 MPEG-4 “Simple Profile” Video Encoder incorporates a number of hardware blocks for the acceleration of key compute-intensive MPEG-4 video compression algorithms, including motion estimation. The same modular architecture is performance-scaleable to more compute-intensive MPEG-4 profiles, such as “Advanced Simple Profile” (ASP). Key component blocks for motion estimation, bitstream packing, pixel compression, and video pre-processing are also available as standalone hardware-accelerator cores for the rapid development of MPEG-4

People News

Verisity Ltd. expanded its international operations in Europe and Asia by appointing Coby Hanoch to vice president and general manager of international operations, and Sean Redmond to vice president of European sales.

Hanoch joined Verisity as a founding member in 1996 and has most recently served as Verisity's vice president and general manager of European operations. Prior to joining Verisity, Hanoch was director of design automation and verification at nSOF, Ltd. in Israel. Before that, Hanoch held similar positions at ACRI, SARL (Advanced Computer Research Institute) in France, as well as National Semiconductor. Hanoch holds a Bachelor's of Science degree in computer engineering from the Israel Institute of Technology (Technion) in Haifa, Israel.

Redmond joined Verisity as the area director for Northern Europe in 2000 and in his new role, is chartered with continuing the company's outstanding success and penetration in Europe. Prior to coming on board at Verisity, Redmond held sales management and engineering positions at IP-DA, Galax! (a subsidiary of Avant!), COMPASS Design Automation, VLSI Technology, and Philips Semiconductors. He earned a Bachelor's degree in electronic engineering from Brighton University, an M.S. in digital systems from Kings College, London University, and an M.B.A. from Henley Management College.

Also part of the expansion, Verisity has partnered with an impressive array of regional distributors to assist with the sales and adoption of Verisity technology and methodology. Verisity is represented by CyberTec and LSI Systems in Japan; Maojet Technology Corporation in Taiwan; KT Design in Korea; Reliant Electronic Design Services Pte Ltd. in Singapore; and CMR Design Automation Ltd. in India.

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-- Ann Steffora, Contributing Editor.

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