November 18, 2002
Cadence and Synopsys Settle Longstanding Avant! Trade Secret Theft Case
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Ann Steffora - Contributing Editor

by Ann Steffora - Contributing Editor
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Just when it appeared they would actually take it to a courtroom trial, Cadence Design Systems, Inc. and Synopsys, Inc. settled the lengthy litigation known formally as “Cadence Design Systems, Inc. et al. v. Avant! Corporation et al.,” in the United States District Court for the Northern District of California.

Per the settlement, Cadence will be paid $265 million. In addition, Cadence, Avant! and Synopsys, as the acquirer of Avant! have entered into reciprocal licenses covering the intellectual property at issue in the litigation.

Ray Bingham, president and CEO of Cadence said the settlement “underscores the integrity of the laws that protect and thereby enable innovation. With the litigation behind us, our resources -- and those of Synopsys -- can be more focused on providing solutions for the technology challenges faced by our customers. I believe that the electronic design industry now can move forward in a spirit of cooperation and healthy competition.”

Dr. Aart de Geus, chairman and CEO of Synopsys add that while they do not condone the actions taken against Cadence in the past by Avant!, they also acknowledge the damage that it has caused to Cadence. “Today's agreement puts this matter to rest for good. We are pleased that we were able to work constructively with Cadence in order to resolve this matter. We are hopeful that the settlement will open a new chapter to a more mature and healthier electronic design industry going forward.”

Cadence will be paid $265 million in two installments: $20 million to be paid on or before November 22, 2002, and $245 million to be paid on or before December 16, 2002. The amount will be paid by Illinois National Insurance Company, a subsidiary of the American International Group (AIG), insurer for Synopsys, under an insurance policy purchased by Synopsys upon the completion of its acquisition of Avant!

Product News

Aptix Corporation rolled out Aptix Prototype Studio, which the company reported extends the benefits of Aptix prototyping technology to developers of custom multi-FPGA PCBs and has support for Aptix prototyping products: System Explorer and Software Integration Station (SIS). It provides a complete RTL to pre-silicon prototype (PSP) flow, regardless of whether the target is a hardwired or reconfigurable PSP.

Aptix Prototype Studio includes Aptix Design Pilot, supports partitioning a monolithic SoC design across multiple FPGA devices, works within the pin constraints of the FPGAs, maps SoC constructs like gated clocks into structures more appropriate for FPGAs, and debugs with the PSP when problems are uncovered in the design, the company said. Aptix Prototype Studio supports the latest Xilinx FPGA devices.

Aptix Prototype Studio is available in three forms.
  • Aptix Prototype Studio/PCB is available to designers targeting only hardwired PCBs.
  • Aptix Prototype Studio/Pro supports Aptix traditional reconfigurable prototyping products, System Explorer and Software Integration Station.
  • Aptix Prototype Studio/Enterprise supports all hardware targets.
  • Additionally, the link from the Aptix prototype database to a hardwired PCB utilizes FPGA Connector from Translogic, which automatic creates homogeneous and heterogeneous symbols to interface to industry standard schematic editors, in order to reduce the setup requirements for symbol creation into minutes. The link converts HDL descriptions into pin constraints for FPGAs and includes version management to ensure database consistency and accuracy. This use model promotes parallel engineering efficiency for schematic entry, FPGA place-and-route and board layout, the company said.

    XYALIS introduced GTsmooth, a hybrid metal-fill tool to address CMP issues. GTsmooth uses a model-based approach to identify where dummies must be inserted and follows a rules-based approach to determine how to insert dummies, to minimize thickness variation over chips and wafers, limit CMP effects and increase yield.

    To determine areas where dummy tiles need to be inserted, GTsmooth evaluates the thickness variation over the chip with a proprietary post-CMP thickness estimator, based on XYALIS' years of experience in the CMP domain. The GTsmooth approach is highly flexible and supports any process, since users may plug-in their own post-CMP thickness estimation function, based on the foundry expertise.

    To limit the number of added dummies, reduce the parasitic capacitance variation and minimize performance degradation, XYALIS has implemented a patented algorithm for metal-fill that makes sure that a minimum number of dummies are only added where needed. GTsmooth inserts up to 95 percent less tiles than rules-based tools for maximum yield improvement, the company said.

    GTsmooth inserts a small number of tiles, regularly spaced, so that the computation time is fast without database explosion, enabling designers to insert dummy tiles early in the design process and take their parasitic effects into account during timing verification.

    A last dummy tile insertion step is usually required at wafer level just prior to manufacturing after the process engineer adds test and alignment features to sawing lines. This last modification to the layout breaks the regularity and dramatically increases the size of the wafer-level database. XYALIS' optimizations in terms of computation time, memory and disk usage allow GTsmooth to handle such wafer-level dummy tile insertions.

    0-In Design Automation announced CheckerWare monitors for the AGP 8x, HyperTransport, InfiniBand and RapidIO standards. Leading IC design teams and ABV users can increase verification productivity by utilizing these pre-verified Verilog register transfer level (RTL) monitors to validate compliance with the latest protocol and interface standards, the company asserted.

    CheckerWare monitors are developed with leading customers as part of 0-In's continuing commitment to promote industry standards through the support of open standards. The capabilities of 0-In monitors include formal tool support, testbench and simulator independence, and interoperability with all tools in existing verification environments. Using 0-In's CheckerWare monitors, designers eliminate the time spent on developing and debugging protocol monitors and are free to devote more time to design and verification.

    CheckerWare monitors certify that the designs conform to interface standards and enable products to be interoperable with all products that support these standards. During simulation, CheckerWare monitors warn users of any protocol violations and generate structural coverage statistics to measure testbench efficacy. The same monitors serve as targets and constraints to guide formal verification tools, including the 0-In Search dynamic formal verification tool.

    People News

    Ewald Detjens assumed the role of CEO at Circuit Semantics Inc. Detjens is founder of synthesis provider Exemplar Logic Inc., now part of Mentor Graphics Corporation. In a related move, Detjens has restructured Circuit Semantics to grow the business, increase revenue, expand the customer base and extend its product offerings. Jose Torres has become Circuit Semantics' vice president of marketing.

    Detjens, a resident of San Francisco, founded Exemplar Logic in 1987. Mentor Graphics acquired Exemplar Logic in 1995, where he remained through 1997. Detjens became a private seed investor in various software companies until January 2002, when he became interim CEO of Bridges2Silicon. Previously, Detjens worked for Philips Research Labs and STC Computer Research. A graduate of the University of California at Berkeley, Detjens holds a Bachelor of Science Degree in Computer Science and a Master of Science Degree in Electrical Engineering.

    ReShape, Inc. announced that Professor Andrew B. Kahng, Ph.D., of the University of California at San Diego, has joined the company's technical advisory board. Kahng is Professor of Computer Science & Engineering and Electrical & Computer Engineering at UCSD. He actively researches VLSI physical design, the design-manufacturing interface, and design process optimization; he also leads initiatives in CAD-IP reuse, technology extrapolation, and metrics within the Gigascale Silicon Research Center (GSRC).

    Kahng chaired the Design Technology Working Group for the 2001 and 2002 editions of the International Technology Roadmap for Semiconductors (ITRS), and defined the physical design roadmap as a member of that working group for the 1997, 1998 and 1999 renewals of the ITRS. Full biographical details for Kahng can be found at

    ReShape's TAB membership also includes Forest Baskett, Ph.D., Venture Partner and former Silicon Graphics, Inc. CTO; Mark Horowitz, Ph.D., Professor Electrical Engineering, Stanford University and Rambus, Inc. founder; Kurt Keutzer, Ph.D., Professor Electrical Engineering at U.C. Berkeley, former CTO at Synopsys, Inc.; and Richard Newton, Ph.D. Professor and Dean U. C. Berkeley, School of Engineering.

    Magma Design Automation Inc. named Dr. Ron Rohrer to the position of chief engineer, reporting to Magma President and COO Roy E. Jewell. Rohrer, a long-time EDA visionary, joined Magma in January as an adviser on corporate strategy and will now work full time for the company, with principal responsibility in advanced product research.

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    -- Ann Steffora, Contributing Editor.

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