November 25, 2002
Outlook is Up-beat as COT Panel Offers Constructive Advice
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Panel Backs off of Moore's Law
On a day that Wall Street dramatically posted its largest point gain in many months, a panel of CEOs representing various nodes along the semiconductor design and manufacturing chain spoke optimistically about economic recovery and proved determinedly bullish about the future of the technology sector.
The panel included Jacques Benkoski, President and CEO of Monterey Design Systems, Levy Gerzberg, President and CEO of Zoran, John Bourgoin, Chairman and CEO of MIPS Technologies, Mark Templeton, President and CEO of Artisan Components, Jack Harding, Chairman, President and CEO of eSilicon, and Yoav Nissan-Cohen, Co-CEO of Tower Semiconductor.
Hosted in Santa Clara by EDA vendor Monterey Design and moderated by the ever-enthusiastic Erach Desai, electronics analyst at American Technology Research, the group attempted to answer the question posed by Monterey's Benkoski – Has the “No Economy” Killed IC Design?
the costs of functional design, physical design, and mask lay-out versus the subsequent revenues associated with volume production. Benkoski pointed out that in today's emerging technologies, however – at 90 nanometers and below – that ratio between development and volume production becomes unacceptable and devoid of adequate profit margins. These weakened profits are adding to the woes of the semiconductor industry, he said.
Benkoski suggested that a COT (customer-owned tooling) flow might offer a solution to the dilemma posed by the technically-challenging nanometer process technologies by stimulating a more efficient design flow, tighter integration between design and manufacturing, and lower NRE (non-recurring engineering) and production costs. In Benkoski's scenario, foundries would begin to adopt a broader role in the design chain akin to the fabless ASIC model. He challenged the EDA industry to rethink their existing business models and industry strategies, “to roll up our sleeves, and make it happen.”
there, “the ASIC model still works.”
Subsequent speakers, though wandering off-topic a bit, nonetheless provided insight into the current relationship between various players in the troubled semiconductor industry. Bourgoin, from Star-IP provider MIPS, said the IP model – broad licensing of design cores that shares development costs across a large customer base – should be extended to the concept of “shared R&D,” a concept the other panelist immediately rallied around. He said his market is being driven by customers who already have a design platform in place, while his secondary customer base is just trying to get to market quickly.
Artisan's Mark Templeton, as a spokesman for library vendors, said foundries today may be risking a great deal to try to compete with the likes of IBM and ST Microelectronics by attempting to provide complete services. As the foundries attempt to move aggressively to smaller geometries, he said, they're often unsure if their new design rules will actually work. Customers who are early adopters have to be wary and to determine for themselves what is really manufacturable and which processes they should back off of.
With little acknowledgement that things may have changed over the last several years, eSilicon's Jack Harding waxed poetic about the need for supply-chain management within the context of a disaggregated semiconductor industry. He said he offers services to customers who need to bridge the communication gap across the various players – thermal and packaging experts, DFT (design-for-test) teams, and a host of other experts who now reside in different corporate entities due to disaggregation. His comments seemed to suggest his market niche has suffered little impact from the tech sector downturn.
“running to a new technology node.”
Desai asked if the industry is now at a point where a particular technology node is going to last a lot longer. The panel agreed, to a man, and seemed distinctly relieved at the prospect.
upon the Synopsys HSPICE technology in the first half of 2003.
memory and compute-intensive audits. SpyGlass provides analysis of Verilog and VHDL code early in the design process.
Agere has extended the capability of Spyglass by providing Agere specific rules for analyzing gate-level netlists for design rule violations in such areas as overloaded drivers, undesired clock interactions, electromigration violations, and IP-specific errors. The Agere-specific rules allow SpyGlass to detect potentially fatal design problems. SpyGlass, with the Agere rules, performs both electrical and topology analysis, identifying areas of poor implementation.
design and analysis tool has being integrated in the ASE design flow. SPECCTRAQuest employs a methodology that allows development of constraints for the interconnect through pre-layout exploration, constraint-driven interconnect implementation, and concurrent validation.
Comit Systems, Inc. announced sales of the Fiesta CVXT Verification Environment, part of an integrated toolset for automatic generation of code and documentation within a compatible verification environment, as well as design entry and verification. Fiesta CVXT Verification Environment exemplifies the trend in tools that link Verilog and tcl by offering the functionality option as an alternative to what have historically been expensive SoC verification tools. The Comit verification environment carries no maintenance fees.
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-- Peggy Aycinena, EDACafe.com Contributing Editor.
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