December 02, 2002
Study Finds IC Vendors need both Design and Manufacturing
Please note that contributed articles, blog entries, and comments posted on are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor

by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Additionally, OCP-IP announced that Verisity Ltd., a supplier of tools and methodology for functional verification, has joined the organization. Mackintosh also commented on the Verisity membership: "We are delighted to have Verisity's support for the industry-standard socket and believe it will help spread the benefits of verification reuse throughout the industry."

OCP-IP offers a complete socket solution to its members including tools, training and technical support necessary for creating intellectual property (IP) cores which are OCP-compliant and ready for SoC integration with other third-party IP.

Synopsys Inc. and Avnet Cilicon, a division of Avnet, Inc., announced an agreement to jointly promote Synopsys' FPGA Compiler II for synthesis of complex FPGA designs. The Synopsys tool is now a part of Avnet Design Service's Avalon Reference Design System. Avnet customers will have access to features in FPGA Compiler II, including block-level incremental synthesis (BLIS) and re-timing.

Xilinx Inc. announced that it is shipping the System Generator for DSP tool v.2.3. The System Generator for DSP tool automatically translates DSP systems developed using MATLAB and Simulink from The MathWorks into optimized VHDL and IP cores for Xilinx FPGAs. The new tool gives designers access to pipelined embedded multipliers using pre-placed input and output registers to achieve improved performance per area of silicon. The new release also supports 3x faster code generation, a dozen-plus reference designs/tutorials, and application notes for creating custom DSP data path peripherals for the IBM CoreConnectbus architecture

Toshiba America Electronic Components, Inc. (TAEC) announced the opening of its seventh U.S.-based design center located in San Diego, CA. The new design center will provide SoC design implementation support and is the second design center opened by the company this year. "Despite being in the midst of a semiconductor recession, we are committed to the SOC business and continue to invest strategically as part of our plan to grow TAEC's share of the North American market," said Richard Tobias, Vice President of the ASIC and Foundry Business Unit at TAEC. Earlier this year, TAEC opened a new design center in Minneapolis, MN, concentrating on mixed-signal development and design
implementation for customers across the United States.

Coming soon to a theater near you

2002 ACM/IEEE International Workshop - If you're quick, you can still make it to the 2002 ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems at the Doubletree Hotel in Monterey, CA, December 2nd and 3rd. Sponsored by ACM/SIGDA in cooperation with IEEE, with additional support from Cadence, IBM, Intel, and Magma, this year's theme is timing and deep-submicron effects in design automation. The conference includes eight sessions during the two-day conference and three additional invited sessions covering timing, design for manufacturability, and emerging
technologies. The keynote address, "Computers without Clocks," will be given by Ivan Sutherland, Vice President and Fellow, Sun Microsystems Laboratories. Sutherland will discuss design and methodology considerations surrounding asynchronous design.

Accellera Seminar - There may be a free lunch after all, at least if you're a member of Accellera. On Thursday, December 5th, you can attend a free seminar for Accellera members at the Santa Clara Marriott - Accellera's Verilog Evolution: An Introduction to SystemVerilog - featuring presentations and tutorials on assertions methodologies from Mentor Graphic's Dennis Brophy, Stu Sutherland of Sutherland HDL, Infinion's Vassilios Gerousis, and Synopsys' Stephen Meier. The all-day event runs from 8:30 AM to 3:00 PM and includes, along with lunch, an EDA Vendor Fair. The conference is sponsored by Synopsys, Mentor Graphics, and Real Intent.
Registration information lives at

edaForum02 - If you're in Germany in the next several days, you'll be able to catch edaForum02 as it convenes in Hanover on December 5th and 6th. The conference is organized by the edacentrum as part of its mission to overcome the design gap by collaborative actions of system and semiconductor companies, EDA vendors and research institutes. In contrast to pure technical workshops, this event will focus on technical challenges and business-related topics helping to optimize the EDA investment. The keynote address will be given by U.C. Berkeley's Richard Newton.
DesignCon 2003 - It's not too soon to be penciling dates into next year's calendar, starting with DesignCon 2003 from the International Engineering Consortium, running January 27th to 30th at the Santa Clara Convention Center. The conference will include the NanoEngineering TecForum on Monday, the 27th and keynotes from NVIDIA's Chris Malachowsky and Semiconductor Research's Ralph Cavin. Conference organizers will present an Executive Forum: "Leadership in Times of Change." Two tracks, one on SoC design and one on high-performance systems, will be operating simultaneously at the conference
and the exhibition hall is always a great place to explore.

DATE 2003 - Also for next year, don't forget DATE 2003 in Munich, Germany. The conference runs from March 3rd to 7th and includes tutorials, master courses, an Embedded Software Forum, a Designers Forum, and sessions highlighting emerging topics in electronic design: scalability trends, security in ambient intelligent applications, test, automotive applications, run-time reconfigurable systems, network processing and RF design for highly integrated communication systems. Two items of particular interest - a tutorial on design-and-test challenges beyond 90 nm and a PCB symposium. The Program Committee reviewed 600 submissions in
choosing the papers and presentations for the technical sessions. Conference organizers report that despite difficult conditions in the global electronics market, over 100 companies will be exhibiting including the leading vendors of EDA and DFT tools.


1st Silicon announced that the company's board of directors has appointed Dr. W. John Nelson as CEO. Nelson, who joined 1st Silicon as COO in May 2002, has been acting CEO since September. He succeeds Claudio G. Loddo. Previously, Nelson was COO of General Semiconductor, President of General Semiconductor's Asia-Pacific operation, and President of General Instrument, Taiwan. He directed the construction of the company's manufacturing site in Tianjin, China. His experience also includes wafer-fab operations at Unitrode and Fairchild Semiconductor, and wafer-fab engineering at Analog Devices.

InTime Software, Inc. announced that Ron Burns has joined the company as Vice President of Worldwide Sales. Burns brings a lengthy track record in electronics and EDA to his new role at InTime. His experience includes sales management positions at Forte, Quickturn (A Cadence company), NeoCAD, Mentor Graphics, Silicon Compiler Systems, and Harris Semiconductor. Most recently, Burns served as Vice President of Sales at Forte where he and the CynApps executive team completed the merger with Chronology.

In the category of ...

Women's work

These days, women and men labor side-by-side in the kitchen to prepare the annual Thanksgiving feast. In honor of Thanksgiving, it seemed intriguing to do a quick, unofficial tally of the number of women currently serving in senior executive roles at fourteen of the leading companies in EDA - statistics tabulated from a simple visit to each company's website.

The results - 4 companies with 0% women execs, 4 companies with 8%, 2 companies with 16 %, 2 companies at 20%, 1 company at 25%, and 1 company at 33% - not too impressive, but there may be reasons why.

First, women rarely major in Computer Science, one of the principle feeder disciplines steering people into leadership roles in EDA. U.C. Berkeley reports that among their current crop of graduate students in Computer Science, approximately 15% are women. Stanford numbers appear to be in the 10% to 15% range and Carnegie Mellon weighs in at 22%. Also, even if women do major in technical fields, they may not consider careers in EDA because the industry is neither widely known nor widely discussed within academia. Finally, women may shy away from start-ups such as those in EDA, preferring the salary and benefits security of larger companies. For whatever the reason, the pipeline is not there
and it's probably inappropriate to expect an increase in the number of women executives in EDA over the next few years.

« Previous Page 1 | 2             

You can find the full EDACafe event calendar here.

To read more news, click here.

-- Peggy Aycinena, Contributing Editor.

Review Article Be the first to review this article

Downstream : Solutuions for Post processing PCB Designs

Featured Video
Senior Electrical Engineer for Allen & Shariff Corporation at Pittsburgh, Pennsylvania
Upcoming Events
IEEE Women in Engineering International Leadership Conference at 150 W San Carlos St San Jose CA - May 21 - 22, 2018
SEMICON Southeast Asia 2018 at New Malaysia International Trade & Exhibition Centre (MITEC) Kuala Lumpur Malaysia - May 22 - 24, 2018
Methodics User Group Meeting at Maxim Integrated 160 Rio Robles San Jose CA - Jun 5 - 6, 2018
IEEE 5G World FOrum at 5101 Great America Parkway Santa Clara CA - Jul 9 - 11, 2018
DownStream: Solutions for Post Processing PCB Designs
TrueCircuits: IoTPLL

Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise