January 20, 2003
Herscher lives for the moment at Cadence
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Peggy Aycinena - Contributing Editor


by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Monterey Design Systems announced that the company would be offering the entire Monterey product line, including the Dolphin RTL second generation RTL-to-GDSII product, in Russia through a distribution agreement with Streamline Design Solutions.
Neolinear announced a distribution agreement with Cadence Design Systems, Inc. for representation throughout Asia including China, Taiwan, Korea, Hong Kong, India, Australia and ASEAN. Effective immediately, Cadence will sell and support all Neolinear products, including NeoCircuit, NeoCircuit-RF and NeoIP.
0-In Design Automation announced the addition of Mentor Graphics to the 0-In Check-In Partner Program. 0-In has developed an assertion-based verification (ABV) interoperability strategy based on Verilog RTL and support for Accellera standards. Through the Check-In Program, 0-In and its EDA partners collaborate to provide customers with testbench- and simulator-independent assertions throughout the design and verification cycle - from the block-level to the system-level. The 0-In Check-In Partner Program will provide customers of 0-In and Mentor Graphics the ability to use 0-In assertions across Mentor Emulation Division's accelerated simulation and emulation products.
Prover Technology announced that its equivalence checking technology, Prover eCheck now interoperates with the Debussy Knowledge-Based Debug System from Novas Software, providing an RTL-to-gate equivalence checking solution for verifying design transformations. Errors found by Prover eCheck are analyzed in the user's existing Debussy debugging environment. Additionally, Prover has joined the Novas Software Harmony Program to formalize the relationship between the companies. Novas established its Harmony program in 1999 to lower the cost of EDA tool interoperability, and to provide developers of verification and other tools with Debussy licenses, engineering support for
integration efforts, and ongoing support for mutual customers.

Pulsic Ltd. announced it has closed $5.5 million in first-round investment financing from Prime Technology Ventures and Index Ventures. Pulsic was launched in January 2002. The company's Lyric product line is a shape-based IC routing environment for complex analog, custom digital, mixed-signal and SoC designs.
Synopsys, Inc. announced that Silicon Integrated Systems Corp. (SiS) completed the design of its Xabre 600 high-performance graphics chip using Synopsys' Physical Compiler to assist with timing convergence and produced a 25-percent improvement in clock speed. The Xabre 600 chip uses SiS's 0.13-micron process technology, has 30 million transistors, and an engine and memory clock speed of over 300 MHz. Using the previous design flow, the Xabre design averaged three-to-five iterations between synthesis and place-and-route. Using Physical Compiler, SiS reports reducing the turnaround time from several weeks to several days.
Also from Synopsys - The company announced that Agilent Technologies, Inc. has standardized on PrimeTime SI for signal integrity analysis in its 0.13-micron ASIC design flow for the embedded core chips used in Agilent's Hardcopy printer products. Timing and signal integrity closure are difficult in SoC designs at 0.13 microns and below - a range where signal integrity effects include crosstalk, noise, and IR drop. Agilent reported success in integrating PrimeTime SI into its existing PrimeTime-based (timing sign-off tool) flow and reduced tape-out failures due to signal integrity effects.

Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC) and Cadence Design Systems, Inc. announced efforts to create an integrated design capability to accelerate time-to-volume for nanometer design. As a result, Cadence becomes the first full-line distributor of TSMC's internally developed standard-cell and I/O libraries, and memories. Additionally, the two companies announced they will collaborate to integrate TSMC's 0.15-micron, 0.13-micron, and Nexsys 90-nanometer standard cell and I/O libraries, and memories with Cadence's Encounter design flow. This integration is supported by Cadence Design Foundry design services, a member of TSMC's Design Service Alliance. TSMC's
standard cell and I/O libraries for TSMC's 0.15-micron, 0.13-micron and Nexsys 90-nanometer processes are available from Cadence now. TSMC's memories will be available from Cadence starting in Q2 2003.

Texas Instruments Inc. (TI) introduced two synchronous buck drivers for high-efficiency, non-isolated, low output voltage DC/DC converters. Providing up to 40-percent improved heat dissipation, each driver can be used with 12V or 5V input systems, or with 3.3V input systems with higher bias rail, to generate lower output voltages for CPUs, general computer, data communications, telecommunications, and general merchant power supply applications. John Vigars, Product Line Manager for TI's power supply control products said, “Typical gate drivers with adaptive delay techniques wait for one switch to be turned off before turning on the other to prevent cross-conduction, which
always results in an inherent dead-time where body diode conduction losses occur. With today's low-output voltages and higher operating frequencies requirement, these body-diode losses become increasingly significant. These new drivers quickly find the optimal overlap between both gate drive transitions to eliminate the body-diode conduction and adjust for temperature variations and load-dependent delays.”
Also from Texas Instruments - The company introduced a single-chip four-channel wideband digital downconverter and upconverter for radios in 3G wireless base transceiver systems, offering both functions in a single package. Targeted mainly towards CDMA2000 and W-CDMA base station systems, the new device also offers digital radio performance for other applications such as wireless repeaters, cable modem radios, wireless instrumentation, and defense-based digital radio systems. TI's GC5016 offers150 MSPS clocking, flexible wideband digital filtering, many input-output interfacing options, and low power dissipation. The product can provide either four channels of digital downconversion,
four channels of digital upconversion, or two channels of downconversion and two channels of upconversion simultaneously, meaning that base station radio engineers need to become familiar with only one device for both downconverter and upconverter functions.
Toshiba America Electronic Components, Inc. (TAEC) detailed its SOC strategy and announced the launch of its 90-nanometer TC300 family based on the Toshiba CMOS process, CMOS4. With 11 layers of copper wire and low-k insulating material, TC300 delivers up to a 100-percent increase in gate integration, a 20-percent increase in gate speed, and a 50-percent reduction in power consumption, compared to the previous generation 0.13-micron process technology (TC280). Toshiba is now accepting designs and the first customer samples have been shipped.
Also from TAEC - The company and its parent company, Toshiba Corp., announced a family of 128-megabit PSRAMs, which combine the most features of SRAMs and DRAMs to provide designers of wireless and portable communication products with a low-power memory solution. The new generation of Toshiba PSRAMs feature an 8-word page access mode for high-speed access and performance improvement. The devices also support partial array refresh and are capable of additional reductions in standby power consumption.
Vitesse Semiconductor Corp. announced it is the first company to provide InP (Indium Phosphide) HBT (heterojunction bipolar transistor) foundry services through MOSIS, a leading provider of low-cost prototyping and small-volume production services for IC development. By working directly with MOSIS, customers will have access to Vitesse's proprietary InP VIP-1 technology. The VIP-1 process includes high performance SHBT (single HBT) devices with other active and passive devices, and multiple levels of metal interconnect. The VIP-1 process offers circuit designers both high-speed and high-voltage operation suitable for digital, analog, and RF circuits at 10GHz or higher. The process
has been qualified for production usage and has an expected turnaround time for prototype circuits of 13 weeks, two times faster than competitive technologies such as SiGe. InP foundry services from Vitesse and MOSIS are available immediately, with quarterly fabrication runs initially planned.
Xilinx, Inc. announced that Marconi plc selected Xilinx Virtex-II Platform FPGAS for gigabit Ethernet traffic over its SONET (synchronous optical network) and SDH (synchronous digital hierarchy) products for optical network applications. The new Marconi products offer improvements in core and metropolitan networks, as well as an evolutionary path towards integrated optical networking. “SDH is used in telecommunications networks throughout the ETSI-standard region, covering Europe, Asia Pacific, South America, the Middle East and Africa,” according to Alberto Mari, Data Interface Product Director at Marconi. “By using a reconfigurable solution in our
next-generation products, we were able to speed up the development cycle and upgrade the functionality of the chip.”
Also from Xilinx - the company announced the availability of a new adaptive I/O solution, enabling system designers to automate the process of fine tuning serial I/O to achieve maximum system performance. The solution includes three new reference designs addressing applications such as communication line cards. The reference designs reflect Xilinx's commitment to support the industry trend toward serial connectivity - the Serial Tsunami initiative - which involves companies across a range of industries working to reduce system costs, simplify system design, and provide scalability to meet new bandwidth requirements.

Zarlink Semiconductor unveiled what the company describes as the world's first off-the-shelf, single-chip radio transceiver for cell phones used in multi-band, multi-mode, 2G and 2.5G digital cellular networks. Zarlink's ZL20250 chip is targeted at handsets for GAIT overlay networks that add GSM capability and mobile Internet data services to existing TDMA/AMPS wireless infrastructure. Multi-mode GAIT cellular networks are being deployed extensively across North America. Zarlink's new transceiver eliminates about 60 separate components from GAIT cell phones, shrinking the size of the radio by more than half.


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-- Peggy Aycinena, EDACafe.com Contributing Editor.




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