January 20, 2003
Herscher lives for the moment at Cadence
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Monterey Design Systems announced that the company would be offering the entire Monterey product line, including the Dolphin RTL second generation RTL-to-GDSII product, in Russia through a distribution agreement with Streamline Design Solutions.
Neolinear announced a distribution agreement with Cadence Design Systems, Inc. for representation throughout Asia including China, Taiwan, Korea, Hong Kong, India, Australia and ASEAN. Effective immediately, Cadence will sell and support all Neolinear products, including NeoCircuit, NeoCircuit-RF and NeoIP.
0-In Design Automation announced the addition of Mentor Graphics to the 0-In Check-In Partner Program. 0-In has developed an assertion-based verification (ABV) interoperability strategy based on Verilog RTL and support for Accellera standards. Through the Check-In Program, 0-In and its EDA partners collaborate to provide customers with testbench- and simulator-independent assertions throughout the design and verification cycle - from the block-level to the system-level. The 0-In Check-In Partner Program will provide customers of 0-In and Mentor Graphics the ability to use 0-In assertions across Mentor Emulation Division's accelerated simulation and emulation products.
integration efforts, and ongoing support for mutual customers.
Pulsic Ltd. announced it has closed $5.5 million in first-round investment financing from Prime Technology Ventures and Index Ventures. Pulsic was launched in January 2002. The company's Lyric product line is a shape-based IC routing environment for complex analog, custom digital, mixed-signal and SoC designs.
Synopsys, Inc. announced that Silicon Integrated Systems Corp. (SiS) completed the design of its Xabre 600 high-performance graphics chip using Synopsys' Physical Compiler to assist with timing convergence and produced a 25-percent improvement in clock speed. The Xabre 600 chip uses SiS's 0.13-micron process technology, has 30 million transistors, and an engine and memory clock speed of over 300 MHz. Using the previous design flow, the Xabre design averaged three-to-five iterations between synthesis and place-and-route. Using Physical Compiler, SiS reports reducing the turnaround time from several weeks to several days.
Also from Synopsys - The company announced that Agilent Technologies, Inc. has standardized on PrimeTime SI for signal integrity analysis in its 0.13-micron ASIC design flow for the embedded core chips used in Agilent's Hardcopy printer products. Timing and signal integrity closure are difficult in SoC designs at 0.13 microns and below - a range where signal integrity effects include crosstalk, noise, and IR drop. Agilent reported success in integrating PrimeTime SI into its existing PrimeTime-based (timing sign-off tool) flow and reduced tape-out failures due to signal integrity effects.
standard cell and I/O libraries for TSMC's 0.15-micron, 0.13-micron and Nexsys 90-nanometer processes are available from Cadence now. TSMC's memories will be available from Cadence starting in Q2 2003.
always results in an inherent dead-time where body diode conduction losses occur. With today's low-output voltages and higher operating frequencies requirement, these body-diode losses become increasingly significant. These new drivers quickly find the optimal overlap between both gate drive transitions to eliminate the body-diode conduction and adjust for temperature variations and load-dependent delays.”
four channels of digital upconversion, or two channels of downconversion and two channels of upconversion simultaneously, meaning that base station radio engineers need to become familiar with only one device for both downconverter and upconverter functions.
Toshiba America Electronic Components, Inc. (TAEC) detailed its SOC strategy and announced the launch of its 90-nanometer TC300 family based on the Toshiba CMOS process, CMOS4. With 11 layers of copper wire and low-k insulating material, TC300 delivers up to a 100-percent increase in gate integration, a 20-percent increase in gate speed, and a 50-percent reduction in power consumption, compared to the previous generation 0.13-micron process technology (TC280). Toshiba is now accepting designs and the first customer samples have been shipped.
Also from TAEC - The company and its parent company, Toshiba Corp., announced a family of 128-megabit PSRAMs, which combine the most features of SRAMs and DRAMs to provide designers of wireless and portable communication products with a low-power memory solution. The new generation of Toshiba PSRAMs feature an 8-word page access mode for high-speed access and performance improvement. The devices also support partial array refresh and are capable of additional reductions in standby power consumption.
has been qualified for production usage and has an expected turnaround time for prototype circuits of 13 weeks, two times faster than competitive technologies such as SiGe. InP foundry services from Vitesse and MOSIS are available immediately, with quarterly fabrication runs initially planned.
next-generation products, we were able to speed up the development cycle and upgrade the functionality of the chip.”
Also from Xilinx - the company announced the availability of a new adaptive I/O solution, enabling system designers to automate the process of fine tuning serial I/O to achieve maximum system performance. The solution includes three new reference designs addressing applications such as communication line cards. The reference designs reflect Xilinx's commitment to support the industry trend toward serial connectivity - the Serial Tsunami initiative - which involves companies across a range of industries working to reduce system costs, simplify system design, and provide scalability to meet new bandwidth requirements.
You can find the full EDACafe event calendar here.
To read more news, click here.
-- Peggy Aycinena, EDACafe.com Contributing Editor.
Be the first to review this article