January 20, 2003
Herscher lives for the moment at Cadence
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor

by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Simplex acquisition brings powerful technology and leadership in-house
Penny Herscher's a tough guy and she knows it. She's tough mentally and she's tough physically. She's also smart and hard driving and funny and warm. Yeah, yeah - and she's a wife, a mom, a daughter, a sister and a friend for those who are uncomfortable with describing a woman as “tough.” If Herscher were a man, a senior executive, and subject of this profile, nobody would need to know if he was a husband, a dad, a son, a brother or a friend. But this is the real world and we're all who we are - there's no use pulling any punches. Penny's a tough guy and she's a woman. And these two things combined make her the right person for the hat she's currently wearing, that of Executive
Vice President and Chief Marketing Officer at Cadence Design Systems, Inc. in San Jose, CA.

And in this corner - more consolidation
Synopsys, Inc. and Numerical Technologies, Inc. announced on January 13th that they have signed an agreement for Synopsys to acquire all outstanding shares of Numerical's common stock for a cash purchase price of $7.00 per share. Aart de Geus, Chairman and CEO at Synopsys said, “Design-for-manufacturing issues will continue to gain importance as designs inevitably shrink toward the 65-nanometer mark. Combining Numerical's lithography-enabling solutions with Synopsys' design tools will enable us to further reduce costs and manufacturing risk for customers involved in creating smaller, faster, and more power-efficient chips.”
The acquisition will be effected by means of a cash tender offer of all of the outstanding shares of Numerical for a cash purchase price of $7.00 per share, followed by a second-step merger in which Synopsys would acquire any untendered Numerical shares at the same price per share. The total transaction value is approximately $250 million and is expected to close during the Q1 2003.
Numerical Technologies went public in a highly touted IPO in Q2 2000, propelling company founder and then CEO, Y.C. (Bruno) Pati, into a position of mentor and role model for other design automation company executives also hoping to go public. The company's stock valuation, since the heady months after the IPO, has endured a slow decline consistent with the market. Last month, company CEO Larry Hollatz was replaced with an interim President and CEO, Naren Gupta.

Meanwhile, Cadence Design Systems, Inc. announced January 15th that it has acquired Celestry Design Technologies, Inc. Cadence says the acquisition adds to the company's product offerings in silicon modeling, expands its expertise in process and manufacturing technology, and provides customers full-chip circuit simulation technology. Per Lavi Lev, Executive Vice President and General Manager of Cadence IC Solutions business: “This acquisition underscores our commitment to deliver great technology to our customers, and it strengthens our already considerable links to the foundries.”

According to Cadence, the Celestry acquisition is part of the company's strategy to acquire companies whose technologies complement its own product development, to increase its ability to provide customers with end-to-end design solutions, and to advance the Cadence Design Chain Initiative strengthening development relationships throughout the electronics industry. Zhihong Liu, President and CEO of Celestry, has been named a Cadence Corporate Vice President reporting to Yaakov Milstain, Corporate Vice President and General Manager of the Cadence Custom IC group. Cadence says it will retain most of Celestry's employees and will continue to support all of Celestry's customers and products.
Other Industry News

Agere Systems announced a read-channel IC designed for high-capacity desktop and mobile hard disk drives currently under development. The first chip in Agere's family of TrueStore components aims for increased functionality and signal integrity, as well as higher levels of data storage capacity for disk drive manufacturers. The TrueStore RC6500 read-channel allows high areal density - the amount of data per square inch that can be reliably stored on a drive's magnetic platter - through increased signal-to-noise ratio (SNR) performance and is manufactured using a 130-nanometer CMOS process technology. As the industry moves to higher levels of chip integration, read-channels are
crucial for Agere's storage system-on-a-chip (SoC) designs, incorporating other drive functions including an embedded microprocessor, memory and hard disk controller into a single integrated device.
Aldec, Inc. announced the release of Riviera 2002.12. Riviera's cross-platform support provides designers on all operating systems access to fast verification runs regardless of the source language. The Riviera product is based on Aldec's VHDL and Verilog mixed-language simulation technology. The new release has yielded results ranging up to 3x on gate- and timing-level simulations, and includes a new design browser, and new memory viewer allowing designers a graphical representation of how efficiently the memory is working in their designs. Riviera 2002.12 also includes an improved, automated interface to Summit Design's Visual Elite, an enhanced interface to Novas
Debussy with an updated FSDB writer, and overall VHPI/PLI optimization. The new release also includes additional support for PLI (VPI) functions.
Altera Corp.
announced that the BXR-48000 from Marconi plc uses a range of Altera devices, including the Stratix, APEX 20K and Mercury FPGAs to help manage information streams at high rates of throughput over transport infrastructures. The BXR-48000 will allow service providers to manage their voice, video, and data traffic, and offer differentiated Internet protocol (IP) services while protecting legacy revenue streams. “Marconi set out to design a next-generation product that would help service providers define a clear return on investment as they evolve their networks to meet rising levels of mission-critical voice, video, and data traffic," said Tom Murray, vice
president of marketing for Marconi's Broadband Routing and Switching group. The Stratix, APEX 20K, and Mercury FPGAs supplemented the ASICs designed and developed by Marconi in the BXR-48000, and aided in the development of the protocol- and payload-agnostic switch-router.

Analog Design Automation, Inc. (ADA) announced that it has closed $8 million in Series B financing, bringing total funds raised to $17 million. The funds will be used to support and expand ADA's marketing and sales activities and for R&D on the company's Genius optimization and performance trade-off exploration products.

Cypress Semiconductor Corp. announced the release of its timing development tool suite, CyberClocks. The software addresses timing design by introducing a black-box approach to configuring programmable clocks. While traditional software models cater to engineers who understand phase-locked loop (PLL) technology, the black-box approach of CyberClocks enables the designer, without knowledge of the workings of a PLL, to specify input and output clock requirements while the suite computes the optimal configuration. The suite's embedded design rule checking promotes stability in the PLL system under all valid programming conditions and data sheet parameters.
Entrada Software, Inc. and Cimmetry Systems Inc. announced that Entrada has licensed Cimmetry's visualization and collaboration technology to embed in Entrada's eChange Solutions product. Cimmetry's AutoVue allows users to view, markup, and collaborate in real-time on 200+ different document formats from a single interface. Formats supported include: 3D CAD parts and assemblies, 2D CAD drawings and drafts, EDA layouts and schematics, scanned and raster documents, vector files, office documents, and graphics. Entrada's eChange Solutions is a collaborative design change and document management product that provides secure, scalable document control, revision history, and
workflow across a global supply chain.

Intel Corp. delivered six new mobile processors, including the Mobile Intel Pentium 4 Processor-M at 2.4 GHZ, and announced an integrated graphics chipset for the mobile PC processor family: the Intel 852GM. Systems based on the new mobile processors are immediately available from computer makers. The company says the 852GM integrated graphics mobile chipset offers advanced levels of performance and flexibility to PC users. When combined with either the Mobile Intel Pentium 4 Processor or the Mobile Intel Celeron Processor, the chipset delivers double data-rate 266/200 memory capability and a 400 MHz system bus. The chipset includes six integrated USB 2.0 ports and supports mobile
power management features to help extend battery life.

iRoC Technologies announced release of the beta version of M-RoCKIT, a new technology platform for automated generation, interconnection, and insertion of advanced error correcting code (ECC) for protection against bit flips in embedded memories. The company is addressing SoC design issues including increased sensitivity of memories to bit flips for new process technologies, increased Mbits of memories on SoCs, and the 100+ memory types being worked into system chips. The M-RoCKIT platform includes a set of protections including bit parity, ECC techniques, and advanced proprietary solutions. The company reports that for an SoC with more than 100 memories, 50% of
which need to be protected, designers adopting M-RoCKIT reduce design time by 4 times, while saving up to 15% silicon overhead for non-maskable memories and up to 8 times for maskable ones. The M-RoCKIT data sheet is currently available. The beta version will be available for selected customers and alliance partners within Q1/03 while final product pricing and delivery is expected within the first half of 2003.

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-- Peggy Aycinena, EDACafe.com Contributing Editor.

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