February 17, 2003
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor

by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

CoWare Inc. announced that Toshiba Corp. has selected CoWare as the supplier of system-level EDA software for the development and deployment of its Media embedded Processor (MeP) IP. Toshiba credited the CoWare N2C system-level design environment with contributions toward the success of the MeP SoC (system-on-chip) business. MeP is an open, scalable, deeply embedded RISC platform that has been used in the development of SoCs for the digital consumer market and is now open to design partners and SoC customers. CoWare is a member of the MeP Alliance Partner Program, which includes tool providers, software suppliers, design partners, and design houses involved in supporting MeP
and developing MeP-based modules.

Intel Corp. announced a new cellular processor that uses “wireless-Internet-on-a-chip” technology. The highly integrated microchip combines the components of cellular phones and handheld computers onto a single piece of silicon, suggesting advanced functionality, longer battery life, and more innovative phone designs to mainstream phones. The Intel PXA800F cellular processor is a component of the Intel Personal Internet Client Architecture (PCA) and is built using 0.13-micron silicon manufacturing technology. The processor has a high-performance, low-power 312 MHz processor based on Intel XScale technology with 4 MB of integrated on-chip Flash memory and 512 KB of SRAM.
In addition, the processor includes a 104 MHz signal processor with 512 KB of integrated on-chip Flash memory and 64 KB of SRAM. The company says feature-rich phones which include an integrated camera, color screen, and games have multiple components, and that when more of those capabilities are put on a single chip, the functionality of the device increases and production costs decrease.

Lattice Semiconductor Corp. announced the ispGAL22V10A family of ultra-high performance, in-system programmable (ISP) simple PLDs . The ispGAL22V10A family of devices offers performance of up to 455MHz operating frequencies, 2.3ns pin-to-pin delays, and low standby power (less than 300micronW) while supporting I/O standards of 3.3, 2.5 and 1.8 volts. The ispGAL22V10A family has a new 32-pin QFN (Quad Flat-pack No-lead) package along with a traditional 28-pin plastic leaded chip carrier (PLCC) version. The 32-pin QFN is 84% smaller (5x5mm) than traditional PLCC packaging, making it applicable for high-density PCBs used in small-scale consumer and portable electronic applications such
as cellular phones, pagers and PDAs. The company says the ispGAL22V10AC is the industry's first 1.8-volt in-system programmable simple PLD.

Library Technologies, Inc. (LTI) announced that it has joined Synopsys' Milkyway Access Program (MAP-in). MAP-in makes the Milkyway database and environment available to partners and EDA vendors. Through MAP-in, LTI will be able to interface its tools for cell design, cell optimization, noise management, interconnect analysis, block characterization and block modeling with Synopsys' Milkyway database.

Mentor Graphics Corp. announced that Silterra Malaysia Sdn. Bhd. selected Mentor Graphics' Calibre as its internal standard for design rule checking (Calibre DRC), layout versus schematic (Calibre LVS) and optical and process correction functionalities (Calibre OPC). Calibre rule files are available for all current CMOS process technologies, including 0.25-, 0.22- and 0.18-micron, and will be the basis for Silterra's pending 0.15- and 0.13-micron technologies. Silterra will provide the Calibre command files as part of its design kit. Silterra Malaysia is a semiconductor manufacturing service provider offering CMOS process technologies.

M-Systems and Toshiba America Electronic Components Inc., along with its parent company Toshiba Corp., announced the upcoming availability of the Mobile DiskOnChip G3 flash disk, an internal memory product based on M-Systems' x2 technology and multi-level cell (MLC) NAND flash silicon. MLC NAND stores 2 bits of data per cell rather than the 1-bit-per-cell capacity in single-level NAND flash. The DiskOnChip G3 has a single silicon die with 64 megabytes of 0.13-micron MLC NAND flash contained within a 7x10mm ball grid array (BGA) package.

National Semiconductor Corp. announced 10 new high-speed LMH amplifiers for high frequency applications in the communications and video markets. The amplifiers offer ultra-low distortion and wide bandwidth and are members of a new series of high-speed products based upon the VIP10 process - a high-speed, dielectrically isolated, complementary bipolar IC process that utilizes deep trench technology on a bonded wafer for complete dielectric isolation and optimal high-speed amplifier performance.

Novas Software, Inc. was commended by EDN Magazine when the company's Verdi Behavior-Based Debug System was named as a finalist in the EDN 2002 Innovation of the Year Awards competition and included in the Top 100 Products List of 2002. With Verdi, designers can automatically analyze complex design behavior spanning many clock cycles. Technologies qualifying for a 2002 EDN Innovation award must have been introduced and commercially marketed in 2002. Finalists will be honored and winning products announced at an awards ceremony in April.

Oki Semiconductor introduced three product additions to its family of 32-bit, general-purpose microcontrollers featuring ARM architecture, the ML674001, ML67Q4002 and ML67Q4003. The company says its “goal is to make the ARM7 family of microcontrollers the new standard for low-cost 16/32-bit MCU design, much like the 8051 set the standard for 8-bit architecture.”

Prolific, Inc. announced that it has joined Synopsys' Milkyway Access Program (MAP-in). Synopsys' MAP-in allows EDA vendors to link their tools into the Milkyway design database through open APIs. Through MAP-in, Prolific's ProTiming cycle time optimizer and ProGenesis netlist-to-layout cell creation tools will have a tighter interface with Synopsys' Milkyway database and tools.

The Semiconductor Research Corp. (SRC), in conjunction with contest co-sponsors, Cadence Design Systems, Inc., IBM, MOSIS, National Semiconductor Corporation, and NurLogic Design, Inc., announced three Phase One monetary winners and Phase Two contestants in the SRC silicon germanium (SiGe) IC Design Challenge. Fifteen teams have now been selected from the original field of 54 teams representing U.S. and international universities to participate in Phase Two. The contest's objective is to create novel circuit designs that will help accelerate the adoption of the high performance semiconductor SiGe technology by engaging both university faculty and students. According to
the contest sponsors, technologies such as SiGe provide opportunities to create new IC designs that can significantly improve the functionality and performance of a variety of digital and mixed-signal electronic systems. The sponsors hope to leverage the creativity available at leading engineering universities and to prepare graduating engineers with the design expertise needed to compete in IC design careers.

Larry Sumney, SRC's president and CEO said: “I am pleased to announce the top three Phase One winning proposals, although it wasn't easy to pick only three winners. The winning universities are: First Place - University of Washington Team 18, led by Professor David Allstot; Second Place - University of Minnesota Team 51, led by Professor Ramesh Harjani; and Third Place - Cornell University Team 15, led by Professor Kevin Kornegay. Team leaders will be presented a check for their university in the amounts of $7,000, $5,000, and $3,000 respectively.”

The awards were made at the ISSCC 2003 in San Francisco, CA. Phase Two gives fifteen university team finalists the opportunity to fabricate their designs via MOSIS in the IBM 6HP SiGe BiCMOS process and to submit a winning IC design using the enhanced properties of SiGe to improve circuit performance and functionality. The Phase Two winners will be honored at SRC TECHCON 2003 in Dallas, TX in August.

Sequence Design announced that Lightspeed Semiconductor is using Sequence's ShowTime and Columbus-Turbo to increase design runtimes. The company reports performing timing, noise and glitch analyses on a 21-clock, 70,000-instance design in 30 minutes. Lightspeed's designs include the Luminance family of modular array ASICs with upwards of 10 million gates. Designed for a two-metal mask, these devices are built on TSMC's 0.13 micron, 8-layer copper, CMOS process technology.

Sun Microsystems, Inc. announced a redoubled commitment to the UNIX platform. The company says it is extending the benefits of the Solaris OS to x86-based servers with the Solaris 9 x86 Platform Edition, and adds, “While industry competitors abandon UNIX, Sun's strategy guarantees customer continuity and global support for UNIX on its entire line of both SPARC and x86 systems, and on third party x86 systems.”

Synopsys, Inc. announced new implementation and verification IP to accelerate the adoption of the PCI Express interface standard. The DesignWare PCI Express Implementation IP Core is synthesizable and can be configured to address multiple applications, from server and desktop systems to mobile devices. Licensees of the core will receive Verilog source code and example synthesis scripts as well as implementation guidelines for integration, including block placement information, list of critical paths, I/O driver requirements and technology requirements. The DesignWare PCI Express Verification IP aims to simplify testbench
development. It is written in OpenVera and includes bus functional models for endpoint and switch, and a user-extensible monitor to validate protocol conformance and measure coverage.

« Previous Page 1 | 2 | 3 | 4 | 5  Next Page »

You can find the full EDACafe event calendar here.

To read more news, click here.

-- Peggy Aycinena, EDACafe.com Contributing Editor.


Review Article Be the first to review this article
Featured Video
Currently No Featured Jobs
Upcoming Events
RISC-V Workshop Chennai at IIT Madras Chinnai India - Jul 18 - 19, 2018
CDNLive Japan 2018 at The Yokohama Bay Hotel Tokyu Yokohama Japan - Jul 20, 2018
International Test Conference India 2018 at Bangalore India - Jul 22 - 24, 2018
MAPPS 2018 Summer Conference at The Belmond Charleston Place Charleston SC - Jul 22 - 25, 2018
DownStream: Solutions for Post Processing PCB Designs
TrueCircuits: IoTPLL

Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise