February 17, 2003
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and developing MeP-based modules.
In addition, the processor includes a 104 MHz signal processor with 512 KB of integrated on-chip Flash memory and 64 KB of SRAM. The company says feature-rich phones which include an integrated camera, color screen, and games have multiple components, and that when more of those capabilities are put on a single chip, the functionality of the device increases and production costs decrease.
as cellular phones, pagers and PDAs. The company says the ispGAL22V10AC is the industry's first 1.8-volt in-system programmable simple PLD.
Library Technologies, Inc. (LTI) announced that it has joined Synopsys' Milkyway Access Program (MAP-in). MAP-in makes the Milkyway database and environment available to partners and EDA vendors. Through MAP-in, LTI will be able to interface its tools for cell design, cell optimization, noise management, interconnect analysis, block characterization and block modeling with Synopsys' Milkyway database.
Mentor Graphics Corp. announced that Silterra Malaysia Sdn. Bhd. selected Mentor Graphics' Calibre as its internal standard for design rule checking (Calibre DRC), layout versus schematic (Calibre LVS) and optical and process correction functionalities (Calibre OPC). Calibre rule files are available for all current CMOS process technologies, including 0.25-, 0.22- and 0.18-micron, and will be the basis for Silterra's pending 0.15- and 0.13-micron technologies. Silterra will provide the Calibre command files as part of its design kit. Silterra Malaysia is a semiconductor manufacturing service provider offering CMOS process technologies.
M-Systems and Toshiba America Electronic Components Inc., along with its parent company Toshiba Corp., announced the upcoming availability of the Mobile DiskOnChip G3 flash disk, an internal memory product based on M-Systems' x2 technology and multi-level cell (MLC) NAND flash silicon. MLC NAND stores 2 bits of data per cell rather than the 1-bit-per-cell capacity in single-level NAND flash. The DiskOnChip G3 has a single silicon die with 64 megabytes of 0.13-micron MLC NAND flash contained within a 7x10mm ball grid array (BGA) package.
National Semiconductor Corp. announced 10 new high-speed LMH amplifiers for high frequency applications in the communications and video markets. The amplifiers offer ultra-low distortion and wide bandwidth and are members of a new series of high-speed products based upon the VIP10 process - a high-speed, dielectrically isolated, complementary bipolar IC process that utilizes deep trench technology on a bonded wafer for complete dielectric isolation and optimal high-speed amplifier performance.
Novas Software, Inc. was commended by EDN Magazine when the company's Verdi Behavior-Based Debug System was named as a finalist in the EDN 2002 Innovation of the Year Awards competition and included in the Top 100 Products List of 2002. With Verdi, designers can automatically analyze complex design behavior spanning many clock cycles. Technologies qualifying for a 2002 EDN Innovation award must have been introduced and commercially marketed in 2002. Finalists will be honored and winning products announced at an awards ceremony in April.
Oki Semiconductor introduced three product additions to its family of 32-bit, general-purpose microcontrollers featuring ARM architecture, the ML674001, ML67Q4002 and ML67Q4003. The company says its “goal is to make the ARM7 family of microcontrollers the new standard for low-cost 16/32-bit MCU design, much like the 8051 set the standard for 8-bit architecture.”
Prolific, Inc. announced that it has joined Synopsys' Milkyway Access Program (MAP-in). Synopsys' MAP-in allows EDA vendors to link their tools into the Milkyway design database through open APIs. Through MAP-in, Prolific's ProTiming cycle time optimizer and ProGenesis netlist-to-layout cell creation tools will have a tighter interface with Synopsys' Milkyway database and tools.
the contest sponsors, technologies such as SiGe provide opportunities to create new IC designs that can significantly improve the functionality and performance of a variety of digital and mixed-signal electronic systems. The sponsors hope to leverage the creativity available at leading engineering universities and to prepare graduating engineers with the design expertise needed to compete in IC design careers.
Larry Sumney, SRC's president and CEO said: “I am pleased to announce the top three Phase One winning proposals, although it wasn't easy to pick only three winners. The winning universities are: First Place - University of Washington Team 18, led by Professor David Allstot; Second Place - University of Minnesota Team 51, led by Professor Ramesh Harjani; and Third Place - Cornell University Team 15, led by Professor Kevin Kornegay. Team leaders will be presented a check for their university in the amounts of $7,000, $5,000, and $3,000 respectively.”
The awards were made at the ISSCC 2003 in San Francisco, CA. Phase Two gives fifteen university team finalists the opportunity to fabricate their designs via MOSIS in the IBM 6HP SiGe BiCMOS process and to submit a winning IC design using the enhanced properties of SiGe to improve circuit performance and functionality. The Phase Two winners will be honored at SRC TECHCON 2003 in Dallas, TX in August.
Sequence Design announced that Lightspeed Semiconductor is using Sequence's ShowTime and Columbus-Turbo to increase design runtimes. The company reports performing timing, noise and glitch analyses on a 21-clock, 70,000-instance design in 30 minutes. Lightspeed's designs include the Luminance family of modular array ASICs with upwards of 10 million gates. Designed for a two-metal mask, these devices are built on TSMC's 0.13 micron, 8-layer copper, CMOS process technology.
Sun Microsystems, Inc. announced a redoubled commitment to the UNIX platform. The company says it is extending the benefits of the Solaris OS to x86-based servers with the Solaris 9 x86 Platform Edition, and adds, “While industry competitors abandon UNIX, Sun's strategy guarantees customer continuity and global support for UNIX on its entire line of both SPARC and x86 systems, and on third party x86 systems.”
development. It is written in OpenVera and includes bus functional models for endpoint and switch, and a user-extensible monitor to validate protocol conformance and measure coverage.
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-- Peggy Aycinena, EDACafe.com Contributing Editor.
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