February 24, 2003
Virtual Snow Day
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor

by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

In fact, the global downturn has been a boon for the Indian sub-continent as both the EDA and semiconductor companies have closed down many shops in the U.S. and the U.K. and are making huge investments in setting up their centers in India (to compensate for lost R&D capabilities elsewhere). They view India as a low-cost, high-quality producer of manpower and talent. The two facts which support this claim are the cost of the Indian engineer (one-fifth of the U.S. engineer and one-third of the European engineer) and the quality of the Indian engineer by virtue of the country's excellent track record in technology education. (India has produced a large number of engineers, scientists, and

The Indian Institute of Technology (IIT), is a university system of six highly regarded Engineering Institutes, which together make significant contributions towards the EDA industry in terms of producing both developers and users. The major contributors in EDA among the six are IIT-Kharagpur, IIT-Mumbai, IIT-Delhi and IIT-Madras - where IIT-Madras has seen a fast paced growth in this area over the last few years.

Apart from the IITs, there are also other contributing institutions, including the Indian Institute of Sciences (IISc)-Bangalore, Birla Institute of Technological Sciences (BITS)-Pilani, and the Bengal Engineering College (BEC)-Calcutta, which have all been quite active lately in EDA. The above institutions, apart from producing skilled manpower, also engage in active programs of industrial research with the large EDA vendors and semiconductor companies. Over the years, they have developed in-house training processes that are relevant to these industries, as well. Annually, there are approximately 192,000 engineers graduating out of the various Indian engineering institutes, and of those
graduates, fully 40% are trained in disciplines related to IT and IC design - which translates to 80,000 graduates per year.

The technical universities in India use a range of vendor-supplied software, from PCB design tools to IC and FPGA design tools. The universities use all the best tools in the areas of design entry, simulation, and synthesis, etc. - but lack tools which address specialized applications (EMI/EMC, SI, noise, high-speed analysis, or other high-end analysis tools) or the very expensive tools (for instance, back-end tools in some cases). Design tools are acquired by the universities either through government grants or by way of donations from EDA vendors and semiconductor companies. Some of the EDA and semiconductor companies have also set up Design Excellence Centers in various universities
in India.

Design engineers in India are working in both VHDL and Verilog. For example, STMicroelectronics is a global semiconductor giant and a large consumer of EDA tools. The company has a large number of Customer Divisions working on specific customer projects. ST uses both VHDL and Verilog - the decision as to which language is left up to each Group/Division within ST. I see no particular preferences within these divisions for one language over the other. Instead, the preference may be based on the location of the Customer Unit - whether it is a U.S. customer/market or a European customer/market.

Industry News

Agere Systems announced the PayloadPlus APP540, a network processor that integrates four separate chips into one. The company says the new chip will reduce product development costs by 50% compared to equivalent market offerings. Korea-based Electronics and Telecommunications Research Institute is using theAPP540 processor as a basis for Korea Telecom's countrywide next generation network. The new processor integrates a programmable traffic manager, a multi-field classifier search engine, a network processor, and an Ethernet media access controller (MAC) onto a single device with processing speeds at 5 gigabits per second (Gbits/s). The company says classification, traffic
management, and network processing function like three different “traffic police officers” working in unison with separate yet inter-dependent functions. The classifier determines what should be done with the voice, data, or video information entering communications equipment and the network processor obeys processing and forwarding directions the classifier gives it. The APP540 chip is roughly one-fourth the size of a credit card.

Alcatel and Sun Microsystems, Inc. are announcing a new initiative aimed at service providers pursuing enterprise applications over wireless networks. The new project is part of an expanded relationship between the two companies who are working together on the establishment of a multi-device Java technology-based initiative for consumer and enterprise-focused service providers. Alcatel has been using its 3G Reality Centres to allow live tests on 2.5G and 3G network infrastructures while Sun has deployed its own iForce centres to allow end users and partners to test network applications. The companies say their joint effort is “device-agnostic” and is relevant to
devices from both the fixed and wireless worlds.

Also from Sun - The company announced a software test suite intended for Java technology-enabled mobile devices. The company says the worldwide deployment of 75+ million Java handsets over the past two years means there is a need for an off-the-shelf software test suite to replace in-house development and management of multiple tests for multiple handsets. With the Java Device Test Suite, individual handsets can be tested against 5000+ test cases in four different categories - functionality, stress, performance and sandbox security - and will allows users to plug in additional test suites for new APIs. The Java Device test suite is scheduled to be available in June 2003.

Altera Corp. announced the release of version 3.0 of the Nios embedded processor, which includes features based on the Stratix and low-cost Cyclone device families. The Nios version 3.0 includes: user-Configurable Caches, an enhanced SDRAM controller; the Avalon switch fabric; and a new JTAG-based real-time debugger; an integrated development environment; and a network protocol software library.

In related news - Altera announced the availability of the Nios Development Kit, Stratix Edition, which gives embedded designers a design platform for high-bandwidth system designs. The kit includes version 3.0 of the Nios embedded processor and the Stratix EP1S10 device. The kit also includes Quartus II development software, the SOPC Builder system development tool, and a suite of software development tools, as well as a Stratix development board with the Stratix EP1S10 device, 1Mb of SRAM, 16Mb of SDRAM, 8Mb of Flash, a 10/100 Ethernet port, two serial ports, a Mictor connector for software debug, two expansion headers, power supply, and download cable.

Altium Ltd. announced the TASKING TriCore VX-toolset, an embedded software development toolset intended to increase execution speed and decrease code size up to 10% over the current TASKING TriCore toolset. The new toolset has been developed for Infineon's 32-bit TriCore architecture and uses Altium's Viper compiler framework technology. The toolset is currently in beta testing and full public release is expected in April 2003.

Also from Altium - The company announced today the release of version 3.5 of the TASKING embedded software development toolset for Motorola's DSP56xxx architecture. Version 3.5 offers a redesigned user interface and support for the latest derivatives and evaluation boards, as well as re-arranged menu structures and improved dialogs, including flexible breakpoint configurations, and probe point support to allow data to be retrieved from, and injected into, an application at run-time using I/O simulation.

Applied Wave Research, Inc. (AWR) announced the relocation and expansion of the company's European headquarters at Lyon Court in Hitchin, UK. The new offices will maintain responsibility for managing sales representatives and providing technical support throughout Europe.

Artisan Components, Inc. announced the completion of its acquisition of NurLogic Design, Inc. Under the terms of the agreement, Artisan acquired NurLogic for approximately $5.0 million in cash and $12.7 million in stock. Artisan reserved approximately 822,000 common shares for issuance in connection with stock options assumed in the transaction.

Atmel Corp. announced the release of the AT91RM9200 microcontroller based on the ARM920T 200+ MIPS 32-bit RISC microprocessor from ARM Ltd. The microcontroller is upward-compatible with Atmel's family of ARM7-based microcontrollers and includes various configurations of on- and off-chip memories, along with a set of peripherals for control, communication, and data storage - including a USB host and device, Ethernet 10/100 Base T MAC, and interfaces for a variety of Flash cards. A power management controller permits a range of clock speeds and enables individual peripherals to be powered down when not in use. The AT91RM9200 is available in PQFP208 and BGA256 packages.
Samples are planned from April 2003.

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-- Peggy Aycinena, EDACafe.com Contributing Editor.


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