March 17, 2003
Division of Labor
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor


by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!


One strategy that can help bridge the concept gap between designers and state-of-the-art verification tools is the use of verification IP (either assertion or simulation). Using verification IP does not require the same level of expertise and knowledge as writing them in the first place. They can be an effective mechanism for shortening time-to-first-test and starting a design team on the verification methodology learning curve. Note that the challenges of making a testbench component reusable are different (but as complex) as making a design component reusable - highlighting again the differences between the design and verification methodologies.


c) “Are verification engineers no longer needed?”


Current economic conditions may simply dictate that additional engineers, hired specifically as verification engineers, are no longer affordable - so design teams will have to make do with what they have (and I fundamentally believe that it should force some of the current staff into verification engineering). Assertion-Based Verification also carries the myth that design engineers, by inserting those magic incantations in their RTL code, will suddenly accomplish the bulk of the verification. ABV definitely improves the quality of a design and eases debugging - but they still require a testbench (until formal technology can replace simulators) to exercise the design so the assertions can be
triggered. And assertions can only deal with very localized issues. No assertions can verify the proper reassembly of a set of concurrent out-of-order packet fragments, or the execution of a set of instructions, or the enumeration of a USB network. That still requires a self-checking, high-level (preferably constrainable randomly generated) simulated verification environment.


Some verification will always be performed by the design engineer, the “kick the tires” verification that demonstrates that the module or unit has some hopes of interacting properly in its environment. But the bulk of the verification - creating corner cases, pushing a lot of data and configurations through the system, creating (with the help of the designers) a verification plan and functional coverage model - needs the undivided attention of verification engineers. Having the same engineers doing both design and verification creates a big “hump” in the number of testcases and testbenches that must be written and debugged once the RTL is done and every
one “switches over” to verification - which often requires contractors to meet the original schedule. In contrast, a dedicated verification force can start addressing verification much sooner (usually with the help of functional models) with a more predictable and smoother schedule. Once the RTL is “done,” designers are kept busy by the large number of bugs such a team usually turns up - hopefully many quickly identified and diagnosed using assertions.


(Editor's Note - Thanks, Janick, and to all of you for contributing to this conversation.)




Industry News - Tools & IP


Actis Design, LLC announced AccurateC Rule Generator, which is SystemC-based software that allows designers to create user-defined rules in C/C++, based on project specifications. AccurateC Rule Generator is a companion product to the company's AccurateC Rule Checker, a SystemC-based language rule checker. The company says the tools help engineers to produce design-ready SystemC code and promote design reuse. Additionally, the company announced that is has named PrimeGate Ltd. of Tokyo as its distributor in Japan.


Agilent Technologies Inc. announced that STMicroelectronics selected Agilent's RF design environment (RFDE) for RF/mixed-signal IC design. The company said that STMicroelectronics has begun to upgrade their R&D operations to the Agilent and Cadence Design Systems RFDE-based design flow. RFDE is an RF EDA software platform that integrates RF simulation technologies from Agilent's Advanced Design System into Cadence's analog and mixed signal design flow. RFDE is the first product to result from the Agilent/Cadence alliance.


Altium Ltd. announced the release of CAMtastic DXP and a free ODB++ capable CAM viewer based on this new version. The company says that “CAMtastic DXP is the latest version of Altium's complete CAM verification and editing system that bridges the gap between PCB design and manufacturing and facilitates communication between board designers, fabrication engineers, and their clients.” CAMtastic DXP's new features include bi-directional ODB++ support, advanced panelization, additional DRCs for strengthened data verification, and numerically controlled drill and rout features. The company - headquartered in Australia, with offices in Asia, Europe, and North America - says
that its Windows-based EDA products are positioned in a price/performance range to meet the needs of the population of board designers who do not need high-end tools from Cadence and Mentor.


ARM announced the availability of version 2.0 of its RealView compilation tools, a component of the RealView development solution supporting the new ARM C/C++ EABI (Embedded Applications Binary Interface) standard. New to version 2.0 are ISO C++ support including namespaces, full template support, and real-time type information (RTTI). The compilation tools also provide support for all of the ARM processor families. The ARM C/C++ EABI is a cross-platform standard developed in collaboration with operating system (OS) and tools vendors, which specifies how executables and shared objects work together for OS or other execution environments. The company announced that Symbian Ltd.
is adopting the ARM CC++ EABI system for the Symbian OS.


Barcelona Design Inc. announced the release of version 1.2 of the Prado analog synthesis platform, with an expanded ability to produce a product-specific analog IP block for SoCs. Version 1.2 of the synthesis platform has several new features, including trade-off analysis capabilities, which allow the designer to evaluate performance trade-offs between different automatically synthesized circuits to evaluate system-level requirements.


Cadence Design Systems, Inc. and Semiconductor Manufacturing International Corp. (SMIC) jointly announced that SMIC has qualified one of its first-generation reference flows. The flow incorporates the Cadence Encounter digital IC design platform. The SMIC reference flow was developed using SMIC's 0.18-micron process technology. The companies say that the SMIC-Cadence Reference Flow 1.0 is a complete RTL-to-GDSII flow and includes logic synthesis, simulation, silicon virtual prototyping, and physical implementation. SMIC is the first pure-play advanced IC foundry in China to achieve volume production for 8-inch wafers at 0.25 micron and finer line technologies, and was
established in April 2000. SMIC is a Cayman Islands company based in Shanghai.


Also from Cadence - The company announced a new capability for designing stacked-die packages integrated into the Cadence Advanced Package Designer Suite. The capability supports all phases of design and includes the ability to bond as many dies as desired, to use different spacing rules for each die and quadrant, and to create multiple bonding patterns so that one substrate can handle multiple-die combinations. Advanced Package Designer also provides a capability for combining flip-chip and wirebond die in the same design. The company says that stacked-die packages are particularly common in cell phones, digital cameras, and hand-held devices, which require faster turnaround, higher
levels of integration and the lower costs associated with system-in-package (SiP) products.


And from Cadence, as well - The company announced a new methodology for designing and implementing multigigabit serial interfaces in high-speed PCB systems. Complex multi-board backplane applications can have hundreds or thousands of differential signal pairs, and long cycle times, as engineers perform numerous layout-simulate-fix iterations. Keith Felton, Product Marketing Group Director, PCB Systems Division, says, “This new methodology is a virtual environment that gives the engineer a topological view and allows simulation data to be turned into constraint-driven design.” The environment permits engineers to design a comprehensive set of rules within Constraint
Manager, and then use those rules to drive layout and routing. The new differential signal capability is part of the 15.0 release of the Cadence PCB Expert series design environment.


InnoLogic Systems, Inc. and Novas Software Inc. announced that InnoLogic has joined Novas' Harmony partner program. The two companies say they have a long-standing relationship in that users of InnoLogic's ESP-CV, a product that verifies the functional equivalence between behavioral or RTL models and the SPICE-level netlist of full custom designs, can use Novas' Debussy Debug System to investigate model mis-match. They also say that InnoLogic's membership in Novas' Harmony program will improve the interoperability and support that the companies provide for mutual customers.


InTime Software, Inc. announced that Time Builder, a time-driven hierarchical floorplanner, has been named one of the Top 100 products of 2002 by EDN Magazine. The magazine awards products that generate significant interest because of usefulness and innovation. Time Builder allows any combination of RTL and gates to be input to the system. The tool contains a built-in static timing analyzer and links to synthesis to allow designers to identify timing problems and optimize logic through either gate-to-gate re-synthesis or RTL-to-gate re-synthesis.


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-- Peggy Aycinena, EDACafe.com Contributing Editor.




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