March 17, 2003
Division of Labor
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
One strategy that can help bridge the concept gap between designers and state-of-the-art verification tools is the use of verification IP (either assertion or simulation). Using verification IP does not require the same level of expertise and knowledge as writing them in the first place. They can be an effective mechanism for shortening time-to-first-test and starting a design team on the verification methodology learning curve. Note that the challenges of making a testbench component reusable are different (but as complex) as making a design component reusable - highlighting again the differences between the design and verification methodologies.
c) “Are verification engineers no longer needed?”
triggered. And assertions can only deal with very localized issues. No assertions can verify the proper reassembly of a set of concurrent out-of-order packet fragments, or the execution of a set of instructions, or the enumeration of a USB network. That still requires a self-checking, high-level (preferably constrainable randomly generated) simulated verification environment.
one “switches over” to verification - which often requires contractors to meet the original schedule. In contrast, a dedicated verification force can start addressing verification much sooner (usually with the help of functional models) with a more predictable and smoother schedule. Once the RTL is “done,” designers are kept busy by the large number of bugs such a team usually turns up - hopefully many quickly identified and diagnosed using assertions.
(Editor's Note - Thanks, Janick, and to all of you for contributing to this conversation.)
Industry News - Tools & IP
Actis Design, LLC announced AccurateC Rule Generator, which is SystemC-based software that allows designers to create user-defined rules in C/C++, based on project specifications. AccurateC Rule Generator is a companion product to the company's AccurateC Rule Checker, a SystemC-based language rule checker. The company says the tools help engineers to produce design-ready SystemC code and promote design reuse. Additionally, the company announced that is has named PrimeGate Ltd. of Tokyo as its distributor in Japan.
Agilent Technologies Inc. announced that STMicroelectronics selected Agilent's RF design environment (RFDE) for RF/mixed-signal IC design. The company said that STMicroelectronics has begun to upgrade their R&D operations to the Agilent and Cadence Design Systems RFDE-based design flow. RFDE is an RF EDA software platform that integrates RF simulation technologies from Agilent's Advanced Design System into Cadence's analog and mixed signal design flow. RFDE is the first product to result from the Agilent/Cadence alliance.
that its Windows-based EDA products are positioned in a price/performance range to meet the needs of the population of board designers who do not need high-end tools from Cadence and Mentor.
is adopting the ARM CC++ EABI system for the Symbian OS.
Barcelona Design Inc. announced the release of version 1.2 of the Prado analog synthesis platform, with an expanded ability to produce a product-specific analog IP block for SoCs. Version 1.2 of the synthesis platform has several new features, including trade-off analysis capabilities, which allow the designer to evaluate performance trade-offs between different automatically synthesized circuits to evaluate system-level requirements.
established in April 2000. SMIC is a Cayman Islands company based in Shanghai.
levels of integration and the lower costs associated with system-in-package (SiP) products.
Manager, and then use those rules to drive layout and routing. The new differential signal capability is part of the 15.0 release of the Cadence PCB Expert series design environment.
InnoLogic Systems, Inc. and Novas Software Inc. announced that InnoLogic has joined Novas' Harmony partner program. The two companies say they have a long-standing relationship in that users of InnoLogic's ESP-CV, a product that verifies the functional equivalence between behavioral or RTL models and the SPICE-level netlist of full custom designs, can use Novas' Debussy Debug System to investigate model mis-match. They also say that InnoLogic's membership in Novas' Harmony program will improve the interoperability and support that the companies provide for mutual customers.
InTime Software, Inc. announced that Time Builder, a time-driven hierarchical floorplanner, has been named one of the Top 100 products of 2002 by EDN Magazine. The magazine awards products that generate significant interest because of usefulness and innovation. Time Builder allows any combination of RTL and gates to be input to the system. The tool contains a built-in static timing analyzer and links to synthesis to allow designers to identify timing problems and optimize logic through either gate-to-gate re-synthesis or RTL-to-gate re-synthesis.
You can find the full EDACafe event calendar here.
To read more news, click here.
-- Peggy Aycinena, EDACafe.com Contributing Editor.
Be the first to review this article