March 17, 2003
Division of Labor
Please note that contributed articles, blog entries, and comments posted on are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor

by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Dave Ruggiero, Vice President of Marketing at Pittsburgh Simulation - “Our mission is to dramatically reduce the verification time of complex semiconductor designs and shorten time to market. Getting rid of verification engineers is not a trend we see at the major design houses. Designs that contain millions of cells require the skills of verification engineers. They are an integral part of the design process for large, complex designs. But for smaller, less complex devices, designers alone may be able to address verification.”

Scott Sandler, President at Novas Systems, Inc. - “Our debug systems tools work with all the popular simulators and other verification tools to help users understand the causes of design behavior. We have many design engineers and verification engineers in our customer base. Over the past several years, we've seen a pretty constant mix with respect to how companies organize their design and verification resources. Some create separate groups, some assign engineers specifically to verification for the duration of a project, and some divide the responsibility among the same people over the course of a project. (“You verify mine and I'll verify yours.”) I'd say,
we find about half of our customers dedicate separate people to verification, and we've seen no evidence to support the notion that the mix is changing.”

Robert Hum, Vice President of Design Verification & Test Division at Mentor Graphics Corp. - “Whether or not a verification engineer is part of a team depends on a number of factors, including the type of design, the size of the company, and the existing verification methodology. We see teams with and without verification engineers. The most popular verification tool today is still an HDL simulator, like ModelSim, and most testbenches are still written in VHDL and Verilog. Both designers and verification engineers already have extensive experience with simulators. We think that strategies that expand existing platforms, like adding mixed-language simulation and code
coverage to ModelSim, help users increase verification productivity faster by leveraging their existing knowledge. Simulator companies will continue to add functionality to their tools, because their customers ask them to.”

Dian Yang, President and CEO at InnoLogic Systems, Inc. - “Design and verification engineers have separate and important functions. The design engineer is responsible for interpreting the specification and implementing the design, while the verification engineer is responsible for validating that the design will operate according to its intent, especially within the system context. As migration to 90-nanometer process technology is increasing the complexity of SoC designs, the role of verification engineers continues to be critical. Formal verification tools such as our ESP-CV help the verification engineer to validate the design intent against the design implementation
of critical full custom elements such as memories, datapath, and IOs that are increasingly consuming today's SoC designs.”

Lauro Rizzatti, Vice President of Marketing at EVE (Emulation and Verification Engineering) - “By consensus in the electronic industry, design verification burns 70% or more of the development cycle. The culprit is two-prone - on the one hand, complex and difficult creation of effective test environments, on the other hand, poor to extremely poor processing speed of such test environments. The industry responded in two ways - by inventing new hardware verification languages (HVLs) to help the creation of efficient test suites, and by resorting to hardware-assisted verification solutions to accelerate the execution speed of these test suites. Unfortunately, the above
solutions either require skills that designers are reluctant to develop or resources that are scarcely available to designers.”

“To fully exploit the considerable verification efficacy of an HVL, a designer must learn a new verification language that he/she would rather relinquish to a verification engineer. To effectively use a hardware-assisted solution, the user must spend precious time to setup the hardware-based verification environment, and considerable financial resources to acquire such a system - propositions that a designer would happily hand over to a verification department. The real answer to the problem can only come from a verification solution that combines the power of the HVL methodology, but is made easy to learn, with the performance of emulation, packed in a small footprint and sold for a
fraction of the current emulation prices.”

“Empowered by such a solution, a hardware design department will mirror the development methodology of most software development centers. As each software developer completely verifies his/her piece of code, leaving to a QA team the validation task of the entire software system, so a hardware designer will thoroughly test his/her hardware module and a system verification team will then perform system integration and carry out the time-consuming regression testing.”

“At EVE, we have addressed one of the two causes of the problem by devising ZeBu, a desk-top, high-end emulator. Inserted into every designer's PC/workstation, one or more ZeBu cards can speed up the most complete test environment by several orders of magnitude. We are looking forward to a new breed of HVL solutions that will work in concert with ZeBu and together propose the final answer to the demanding task.”

Steve Wang, Vice President of Marketing at Axis Systems - “The need for verification engineers is not going away, but their place in the design methodology is expanding and moving higher in the design flow. As the industry moves towards the next level of abstraction (Electronic System Level or ESL), these engineers need tools that give them visibility into both hardware and software components of the design much earlier to verify the design is viable along each step of the process. So the tools are not replacing verification engineers, but facilitating their jobs as design and verification become parts of a single methodology.”

Charles Miller, Senior Vice President for Marketing and Business Development at Aptix Corp. - “Our recent customer survey indicates a merging of design and verification groups. (63% say that the Design Group and the Verification Group are one and the same. 31% say that the Design Group and the Verification Group work very closely with each other. 6% fall into the category we call “Other.”) We believe this is driven by increasing design complexity and the need to validate designs under real-world operating conditions. This often requires design knowledge that only resides with the developers.”

The Moderator Weighs In ...

Janick Bergeron, CTO at Qualis, Inc. - “There are many components and facets to the statement. Let me try to address them individually”

a) “Many companies cannot afford to - or choose not to - have a separate individual on the design team who handles verification.”

They choose not to, consciously or otherwise. The work that must be accomplished to design and verify a successful ASIC is constant, regardless of how you choose to distribute it between your engineers. It's a fixed pie. You can let everyone do some design and some verification, or you can let some do all of the design and some do most of the verification. Some distributions will be more efficient than others. But it is a distribution issue, not a technical or financial one.

The other obstacle is cultural. Design is still perceived as more sexy or “fun.” Verification is perceived as boring. Personally, being limited to a coding style imposed by a synthesis technology that is 15 years old is what I find boring and passé. Verification is where the action is - in new methods, tools, and standards. I've been doing verification for 12 years - and I'm always learning something new.

b) “Are the verification tools currently available easily understood and used by design engineers who are NOT verification engineers?”

No more or less than a physical synthesis tool is easily understood and used by a verification engineer. If you are doing a small, low-speed design that does not push the limits of the EDA technology, you can understand and use all of the design and verification tools required to accomplish your job. But for those large, high-speed designs that require an intimate knowledge of the deep-submicron issues and physical synthesis in order to reach timing closure, the complexity of the verification requires expertise in object- or aspect-oriented programming, configuration management and high-level modeling. These skill sets have no overlap and require different background expertise - the former
in device physics, the latter in software engineering.

At the height of the Greek and Roman empires and in the Middle Ages, it was possible for an individual to know and understand all of the human scientific knowledge of the time. But as the quantity and complexity of technology started to increase, individuals had to become specialists. The more complex the technological advances, the more numerous the specialists. ASIC design cannot escape this simple truth of human nature: as design has been split into architects, hardware designer, back-end engineers, manufacturing and test engineers, further splits - such as design and verification - are bound to
occur and must be embraced.

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-- Peggy Aycinena, Contributing Editor.

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