March 24, 2003
EDA in Taiwan & China
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Monterey Design Systems announced it will demonstrate the company's suite of IC design planning, physical synthesis and prototyping, and physical implementation products at the China International Semiconductor and Integrated Circuit Exhibition & Seminar 2003 on March 24th through 26th in Shanghai, China.
Mentor Graphics Corp.'s Accelerated Technology Embedded Systems Division announced a version of the Nucleus RTOS for developers using the OMAP platform from Texas Instruments (TI). The company says that Nucleus developers familiar with ARM programming can now create a range of software applications for multimedia-enhanced devices using TI's OMAP application processors that contain an ARM processor application-programming interface. They add that developers can extend their application by using various Nucleus products including a TCP/IP networking suite, graphics package, and file management system.
Novas Software, Inc. announced that NEC Micro Systems, Ltd. has signed a multi-year, volume purchase agreement for the Novas Debussy Debug System. NEC reports that it first deployed Debussy three years ago as the company's standard IC debug tool. Novas says this new contract confirms Debussy as the preferred debug platform for NEC's development of advanced LSI components, ASIC devices, and SoCs.
ReShape, Inc. announced the company is making an entrance into the EDA industry with the introduction of what the company describes as “the industry's first full-chip implementation system that builds production layouts of multi-million gate SoCs in 24 hours or less.” ReShape's GDS Builder is intended to leverage customers' investments in commercial physical design tools from Synopsys, Cadence, and Mentor Graphics, and to perform full-chip placement, routing, and analysis for complex designs.
The company reports that they have used GDS Builder internally in their own design services work to complete nine commercial tape outs to date, and have used hierarchical layouts to achieve density and performance levels that match the quality of results they had previously achieved using traditional flat design techniques. GDS Builder combines a hierarchical chip implementation process with the company's Action Oriented flow to build design blocks in parallel on Linux servers. GDS Builder uses a layout technique called “channel-less block abutment” to meet requirements for small die size, low latency, and high signal integrity.
The company says that production use of GDS Builder has demonstrated the following advantages over traditional scripted design methodologies - “Two weeks to first full-chip build, fast iterations, instant verification, and fast, predictable tape-outs” The company also reports that the last six tape-outs from GDS Builder were completed in 16 days or less, allowing the physical design team to proceed in parallel with the front-end design team.
company based in Shanghai. The foundry provides design services, mask manufacturing, wafer fabrication, and testing capabilities.
MOST reports that it has been working since early 2000 to organize and implement a project for complex IC design through the HTRDC and the “863” IC Expert Group. The core of the project is an incubator program for IC design companies. Under the agreement with Synopsys, the HTRDC and the “863” IC Expert Group will endorse and standardize an IC design flow based on the licensed Synopsys tool set. Companies participating in the incubator program can use the Synopsys design flow to develop and implement designs.
Jichun Feng, Director of the HTRDC said, “MOST's goal is to foster the growth of IC design companies and the IC design industry in China by providing an environment that aids small start-ups and encourages the ongoing development of design talent and innovative ideas within China. The agreement with Synopsys demonstrates the great progress we are making to accelerate the development of incubators in China's key centers of IC design."
The HTRDC was founded in 1994 and has been approved by the Central Organization Committee of China. It serves various functions, including promoting international cooperation, researching various issues concerned with the industrialization of high and new technology, and developing strategy and policy for high-tech R&D. The HTRDC also provides project management, administration, statistical analysis and technology transfer for the “863” program, as well as consultation and services for MOST in matters pertaining to legal and intellectual property rights.
From Synopsys as well - The company announced that the Information and Communication Networks Division (ICN) of Siemens used Synopsys Physical Compiler to tape out the Switching Element SE9, a complex ASIC designed for extremely fast switching of asynchronous transfer mode (ATM) cells. The first application for the SE9 is in the mobile switching fabric of the ICM Division. Siemens ICN used Physical Compiler's unified synthesis and placement to generate a placed and optimized netlist. LSI Logic, a Siemens ASIC vendor, accepted this placed netlist and completed the design.
Synplicity - The company, along with Lightspeed Semiconductor announced that the two companies have signed a joint technology development agreement to provide support for Lightspeed's 0.13-micron Luminance family of Modular Array ASIC devices. Under the terms of the agreement, Synplicity will develop custom synthesis mapping technology for its Synplify ASIC software, optimized to Lightspeed's Luminance devices. Lightspeed will distribute Synplicity's Synplify ASIC .sel library and accept Synplify ASIC netlists and timing analysis results as input to Lightspeed's back-end place-and-route tools.
Coming soon to a theater near you
DAC Panels - Conference organizers have announced various hands-on tutorials that will, once again, be available at the show in Anaheim, June 2nd to June 5th. The tutorials will emphasize “Signal and Power Integrity Analysis and Methodology” and will allow attendees to solve specific design challenges through guided hands-on experience using current tools and methodologies. Each tutorial focuses on a specific design challenge and encourages attendees to work with the tools, hands-on and in real time. All told there will be seven 3-hour tutorials, each limited to the first 30 enrollees with student-to-workstation ratios of 2:1.
Interconnects at Multi-Gigabit Speeds.” Apache Design Solutions will sponsor “Full-Chip Dynamic Power Grid Methodology from Planning to Verification.” NPTest will sponsor “Signal and Power Integrity Validation with In-Circuit Measurements” (
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-- Peggy Aycinena, EDACafe.com Contributing Editor.
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