March 31, 2003
ASICs versus FPGAs
Please note that contributed articles, blog entries, and comments posted on EDACafe.com are the views and opinion of the author and do not necessarily represent the views and opinions of the management and staff of Internet Business Systems and its subsidiary web-sites.
Peggy Aycinena - Contributing Editor


by Peggy Aycinena - Contributing Editor
Posted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Far and away the best part of being a journalist is having the opportunity to talk to a range of people about a diverse set of topics. This week is no different as three very likable individuals were willing to take time from their busy schedules to explain their perspectives on the current state of affairs in the ASIC versus FPGA controversy - and whether or not there's a controversy there at all.


Bob Payne, U.S. CTO and Senior Vice President/General Manager of System ASIC Technology at Philips Semiconductors, gave one of the keynotes last Tuesday morning, March 25th, at the IEEE International Symposium on Quality Electronic Design (ISQED) in Santa Clara, CA. I talked with Payne later in the day and he said, although there were not as many in attendance at the conference as one might have wished for - many would-be attendees appeared to have canceled travel plans in the first few days of the war - that his talk and those of his fellow keynoters, Toshiba's Susumu Kohyama and Cadence's Aurangzeb Khan, were well received.


He said both Kohyama and Khan appeared to agree, in the main, with his argument that platform-based design has come of age. Payne said that the flexibility offered by the platform design paradigm offers customers everything they need at this point for speedy and reliable product design and differentiation and, hence, eliminates any need to move to an FPGA-based strategy to achieve design cost and scheduling efficiency.


Payne's a relaxed fellow and a fine spokesman for the Philips point of view. He's also, by his own description, an ASIC guy who goes back 30 years in the industry: “I did my first CMOS in 1972.” It's probably safe to say that what Bob Payne doesn't know about the ASIC landscape, isn't worth knowing. And Payne is quite clear - neither Philips nor any of the other large ASIC vendors see any threat from an emerging FPGA market. “We're not feeling at all threatened by any of the FPGA guys. They're generally going after the low-volume customers. The FPGA guys might have thousands of customers, with utilization in the thousands or tens of thousands of units. But the SoC guys are
in a narrow range
of market-share leaders. They're typically building in the million units and beyond region.”


Meanwhile, Payne is equally clear in commending the role that FPGAs play in the prototyping of designs, a role they've played for a long time. “I've always used the expression, 'FPGAs are god's gift to prototyping and you need to use the gift.' I love FPGAs for full-speed, real-time prototyping. Philips' strategy is to build platforms with extensibility. We create IP down on the FPGAs. Then we have it appear as if it's communicating on the busses of the platform on the 'South' chip - which is the FPGA - and actually talking to the structures of the 'North' chip to provide streaming functions, and new peripherals, and so forth.”


“Because we're running at full speed, in real time, we can have the complete software environment on the hardware platform. We get the benefits of an FPGA, but with the performance and density benefits of an ASIC. Philips has adopted a derivative-design friendly approach. So you can prototype, you can use the platform, you can do the whole thing - adding new pieces with functionality, which you can validate with an FPGA. Then you put the cell into high-volume consumer applications with a 100% performance chip. We want to provide our customers with the ability to get new functionality completely validated at full speed, in real time. I'm happy with what's going on in the FPGA because
it provides that ability.”


Philips partners with Xilinx and Altera, and Payne says he respects the work of the FPGA vendors: “We view our relationship with Xilinx and Altera as good relationships. We utilize their parts and have a very harmonious relationship, but we don't view ourselves in competition with them. We're on a completely different playing field from the FPGA guys.”


You'll get a completely different point of view if you have a chance to discuss the ASIC-versus-FPGA thing with Jackson Kreiter, CEO of newly announced Hier Design Inc. - a company committed to providing EDA tools that will “enable programmable devices to obsolete ASIC technology for most standard products.”


Kreiter is adamant that the emerging market for FPGA end-products has arrived - that Hier's phones are ringing off the hook with customers who need his tools to attack the challenges of FPGA design. Kreiter quotes liberally from Gartner Group data that shows a sharp drop in ASIC design starts over the last 3 years and a dramatic increase in PLD/FPGA design starts over that same period. He says we'll see less than 4000 ASIC design starts this year, compared to more than 400,000 FPGA design starts.


It's tempting to ask Kreiter if he's comparing apples to oranges in quoting these numbers - if the ASIC design starts are bigger, more complex, higher performance end-products and some portion of those FPGA designs starts are slated for the prototyping boards. Kreiter is unfazed by the question and argues unequivocally that the “sweet spot in the ASIC market” is undergoing direct, head-on competition from the FPGA vendors.


He says that 17% of the FPGA design starts today are at 500,000 gates and above, while FPGAs sized at 8 million gates with speeds of up to 400 MHz are not uncommon. Kreiter says those statistics should be compared with numbers that show 70% of the ASIC starts are in the 200 MHz range, with 2 million gates and below. The two markets are overlapping, Kreiter says, and the FPGAs are destined to win in the long run.


Kreiter says, “I've talked with many people in the industry who are telling me that ASICs are simply going to die, that ASICs are in big trouble at 90-nanometer [process technologies] and below. Look at Xilinx. They've announced they're going to offer a million-gate FPGA for 25 bucks and I believe that's at 90 nanometers. I'm not saying that [the technology challenges] at 90 nanometers are a slam dunk as yet - we all admit it's not easy - but I do believe that FPGA working parts will emerge at 90 nanometers before ASICs do.”


Then there's the development cost/time issue, according to Kreiter.


He says, “Let's say I've got a customer that wants a product and I decide to make the product on an FPGA. [Essentially], as soon as I program it, I can hand it right to the customer. However, if I do it on an ASIC, I've got to hand the design off to the manufacturing process and then wait months to get a working part. It can take up to half a year to get the product to the customer and, by that time, the customer's demands may have changed. Using an FPGA changes the time it takes between 'freezing' the design and getting it to the customer from many months for an ASIC to a couple of weeks for an FPGA. In fact, we believe that, on average, it takes at least 7 months longer to get an
ASIC
product to market compared to the time it takes to get a [comparable] FPGA product to market.”


Kreiter goes on: “Meanwhile, a lot of start-ups just can't afford to do an ASIC. Lucio Lanza [of Lanza Tech Ventures] tells me that we may reach a point [using next-generation process technology] where it's going to cost $40 million to $50 million to do an ASIC by the time you add in the engineering costs, mask costs, verification, and manufacturing expenses. You'll need to go after a $1.5 billion dollar market to defend those [levels of] development costs. That means a lot of people won't be able to penetrate that product market [if they go the ASIC route] because they'll need millions of customers to justify their initial costs.”


Kreiter does not pretend that the ASIC era is over: “It's true that ASICs are still going to be useful for high-volume production, because they're still cheaper [than an FPGA] when people are tying to milk a product for all it's worth. But, today, very few products get to that point - few products get to that level of market demand. And technology needs to be 'more' disposable, not 'less' disposable. Reprogrammable products are reusable. If an ASIC becomes obsolete - if it's no longer 'good' - you have to throw it away.”


Chuckling, Kreiter says, “I haven't heard of many people melting down an ASIC and reusing the materials. FPGAs, however, can be pulled out and reprogrammed. FPGAs are really the 'green' way to go.”


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-- Peggy Aycinena, EDACafe.com Contributing Editor.


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